公开(公告)号：US20110121442A1

公开(公告)日：2011-05-26

申请号：US12785704

申请日：2010-05-24

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L23/3135 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

摘要： A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.

摘要翻译： 包过程包括以下步骤。 包括多个电路板的电路母板设置在载体上。 提供半导体器件，其中每个半导体器件具有与其相对的顶表面和底表面。 每个半导体器件具有各自具有由半导体器件的底表面暴露的第一端面和第二端面的导电通孔。 半导体器件通过其导电通孔连接到相应的电路板，其底表面面向电路母板。 在每个半导体器件及其相应的电路板之间形成绝缘膏。 在电路母板上形成保护层以覆盖半导体器件。 然后，保护层和半导体器件变薄以暴露每个导电通孔的第一端面。

公开(公告)号：US08446000B2

公开(公告)日：2013-05-21

申请号：US12785704

申请日：2010-05-24

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan ,  Hui-Shan Chang ,  Chia-Lin Hung

IPC分类号： H01L23/02 ,  H01L21/50

CPC分类号： H01L23/3135 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

摘要： A package process includes following steps. A circuit mother board comprising a plurality of circuit boards is disposed on a carrier. Semiconductor devices are provided, wherein each of the semiconductor devices has a top surface and a bottom surface opposite thereto. Each of the semiconductor devices has conductive vias each having a first end surface and a second end surface exposed by the bottom surface of the semiconductor device. The semiconductor devices are connected to the corresponding circuit boards through their conductive vias with their bottom surface facing the circuit mother board. An insulating paste is formed between each of the semiconductor devices and its corresponding circuit board. A protection layer is formed on the circuit mother board to cover the semiconductor devices. Then, the protection layer and the semiconductor devices are thinned to expose the first end surface of each of the conductive vias.

摘要翻译： 包过程包括以下步骤。 包括多个电路板的电路母板设置在载体上。 提供半导体器件，其中每个半导体器件具有与其相对的顶表面和底表面。 每个半导体器件具有各自具有由半导体器件的底表面暴露的第一端面和第二端面的导电通孔。 半导体器件通过其导电通孔连接到相应的电路板，其底表面面向电路母板。 在每个半导体器件及其相应的电路板之间形成绝缘膏。 在电路母板上形成保护层以覆盖半导体器件。 然后，保护层和半导体器件变薄以暴露每个导电通孔的第一端面。

公开(公告)号：US20090127706A1

公开(公告)日：2009-05-21

申请号：US12248562

申请日：2008-10-09

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Tommy Pan

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Tommy Pan

IPC分类号： H01L23/498

CPC分类号： H01L23/49811 ,  B23K35/0233 ,  B23K35/0244 ,  B23K35/22 ,  B23K35/3013 ,  C22C5/02 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/812 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2224/29099 ,  H01L2924/00014

摘要： A chip package structure and process are provided; the structure includes a substrate, a chip, a solder layer and at least a stud bump. The substrate has at least a contact pad, and the chip has an active surface where at least a bonding pad is disposed. The stud bump is disposed on the bonding pad of the chip or on the contact pad of the substrate, and the stud bump joints with the solder layer to fix the chip on the substrate. The stud bump is made of gold-silver alloy containing silver below 15% by weight.

摘要翻译： 提供芯片封装结构和工艺; 该结构包括基板，芯片，焊料层和至少一个凸块。 衬底具有至少一个接触焊盘，并且芯片具有其中设置有至少一个焊盘的活性表面。 螺柱凸块设置在芯片的焊盘或基板的接触焊盘上，并且凸块与焊料层接合以将芯片固定在基板上。 螺柱凸块由含有低于15重量％的银的金 - 银合金制成。

公开(公告)号：US07791211B2

公开(公告)日：2010-09-07

申请号：US12228683

申请日：2008-08-15

申请人： Jen-Chuan Chen ,  Chi-Chih Shen ,  Hui-Shan Chang ,  Tommy Pan

发明人： Jen-Chuan Chen ,  Chi-Chih Shen ,  Hui-Shan Chang ,  Tommy Pan

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K1/111 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/05599

摘要： A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.

摘要翻译： 提供了包括芯片，载体和多个凸块的倒装芯片封装结构。 芯片具有接合表面和其上的多个凸块焊盘。 载体对应于芯片设置并且包括基底和多个预焊料。 衬底具有承载表面和其上的图案化迹线层。 图案化迹线层具有多个迹线，并且每个迹线具有对应于凸块的向外突出的接合部分。 接合部的线宽大于轨迹的线宽。 预焊料分别设置在接合部分上。 凸块设置在凸块焊盘和相应的预焊件之间，使得芯片通过凸块与载体电连接。

公开(公告)号：US20090102047A1

公开(公告)日：2009-04-23

申请号：US12228683

申请日：2008-08-15

申请人： Jen-Chuan Chen ,  Chi-Chih Shen ,  Hui-Shan Chang ,  Tommy Pan

发明人： Jen-Chuan Chen ,  Chi-Chih Shen ,  Hui-Shan Chang ,  Tommy Pan

IPC分类号： H01L23/48 ,  H05K1/00

CPC分类号： H05K1/111 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01079 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2224/05599

摘要： A flip chip package structure including a chip, a carrier, and a plurality of bumps is provided. The chip has a bonding surface and a plurality of bump pads thereon. The carrier is disposed corresponding to the chip and includes a substrate and a plurality of pre-solders. The substrate has a carrying surface and a patterned trace layer thereon. The patterned trace layer has a plurality of traces, and each of the traces has an outward protruding bonding portion corresponding to the bump. The line width of the bonding portion is greater than that of the trace. The pre-solders are disposed on the bonding portions, respectively. The bumps are disposed between the bump pads and the corresponding pre-solders such that the chip is electrically connected to the carrier through the bumps.

摘要翻译： 提供了包括芯片，载体和多个凸块的倒装芯片封装结构。 芯片具有接合表面和其上的多个凸块焊盘。 载体对应于芯片设置并且包括基底和多个预焊料。 衬底具有承载表面和其上的图案化迹线层。 图案化迹线层具有多个迹线，并且每个迹线具有对应于凸块的向外突出的接合部分。 接合部的线宽大于轨迹的线宽。 预焊料分别设置在接合部分上。 凸块设置在凸块焊盘和相应的预焊件之间，使得芯片通过凸块与载体电连接。

公开(公告)号：US08618645B2

公开(公告)日：2013-12-31

申请号：US12711870

申请日：2010-02-24

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan

IPC分类号： H01L23/02

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3135 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/91 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

摘要翻译： 提供包装过程。 粘合剂层设置在载体板上，然后将多个第一半导体器件设置在粘合剂层上。 形成在载体板上的第一模塑料覆盖第一半导体器件的侧壁并填充第一半导体器件之间的间隙，以形成由第一半导体器件和第一模塑料构成的芯片阵列板。 接下来，分别将多个第二半导体器件倒装贴合到第一半导体器件。 然后，形成在芯片阵列基板上的第二模塑化合物至少覆盖第二半导体器件的侧壁并填充第二半导体器件之间的间隙。 随后，芯片阵列板与粘合剂层分离。 然后，沿着第二半导体器件之间的间隙切割第一和第二模塑料。

公开(公告)号：US20110074004A1

公开(公告)日：2011-03-31

申请号：US12711870

申请日：2010-02-24

申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan

发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Tommy Pan

IPC分类号： H01L23/28 ,  H01L21/50

CPC分类号： H01L24/96 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3135 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/91 ,  H01L2224/95001 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

摘要： A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the side walls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the side walls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.

摘要翻译： 提供包装过程。 粘合剂层设置在载体板上，然后将多个第一半导体器件设置在粘合剂层上。 形成在载体板上的第一模塑料覆盖第一半导体器件的侧壁并填充第一半导体器件之间的间隙，以形成由第一半导体器件和第一模塑料构成的芯片阵列板。 接下来，分别将多个第二半导体器件倒装贴合到第一半导体器件。 然后，形成在芯片阵列基板上的第二模塑料材料至少覆盖第二半导体器件的侧壁并填充第二半导体器件之间的间隙。 随后，芯片阵列板与粘合剂层分离。 然后，沿着第二半导体器件之间的间隙切割第一和第二模塑料。

公开(公告)号：US20100327465A1

公开(公告)日：2010-12-30

申请号：US12538338

申请日：2009-08-10

申请人： CHI-CHIH SHEN ,  Jen-Chuan Chen ,  Tommy Pan

发明人： CHI-CHIH SHEN ,  Jen-Chuan Chen ,  Tommy Pan

IPC分类号： H01L23/31 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/75252 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/30105 ,  H05K3/007 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2201/10674 ,  H05K2203/041 ,  H05K2203/1316 ,  Y02P70/613 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A package process is provided. First, a semiconductor substrate is disposed on a carrier, in which a surface of the carrier has an adhesive layer and the semiconductor substrate is bonded to the carrier by the adhesive layer. Next, a chip is bonded on the semiconductor substrate by flip chip technique and a first underfill is formed between the chip and the semiconductor substrate to encapsulate a plurality of first conductive bumps at the bottom of the chip. Then, a first molding compound is formed on the semiconductor substrate. The first molding compound at least encapsulates the side surface of the chip and the first underfill. Finally, the semiconductor substrate together with the chip and the first molding compound located thereon are separated from the adhesive layer of the carrier to form an array package structure.

摘要翻译： 提供包装过程。 首先，将半导体基板设置在载体上，其中载体的表面具有粘合剂层，并且半导体衬底通过粘合剂层结合到载体上。 接下来，通过倒装芯片技术将芯片接合在半导体衬底上，并且在芯片和半导体衬底之间形成第一底部填充物，以在芯片的底部封装多个第一导电凸块。 然后，在半导体基板上形成第一模塑料。 第一模塑料至少封装芯片的侧表面和第一底部填充物。 最后，与芯片和位于其上的第一模塑料一起的半导体衬底与载体的粘合剂层分离以形成阵列封装结构。