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    Semiconductor device with a plurality of mark through substrate vias
    6.
    发明授权
    Semiconductor device with a plurality of mark through substrate vias 有权
    具有多个通过衬底通孔的标记的半导体器件

    公开(公告)号：US08390129B2

    公开(公告)日：2013-03-05

    申请号：US12945134

    申请日：2010-11-12

    申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

    发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Chung-Hsi Wu ,  Meng-Jen Wang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/544 ,  H01L23/481 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/16146

    摘要： The present invention relates to a semiconductor device with a plurality of mark through substrate vias, including a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying the position and direction on the backside surface. Thus, the redistribution layer (RBL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

    摘要翻译： 本发明涉及具有多个标记通过衬底通孔的半导体器件，包括半导体衬底，多个原始通过衬底通孔和多个通过衬底通孔的标记。 原始通过衬底通孔和通过衬底通孔的标记设置在半导体衬底中并从半导体衬底的背面突出。 通过基板通孔的标记在特定位置和/或特定图案上添加，并且用作基准标记，这有助于识别背面上的位置和方向。 因此，不需要再分配层（RBL）或用于实现背侧对准（BSA）的专用设备。

    PACKAGING STRUCTURE
    7.
    发明申请
    PACKAGING STRUCTURE 审中-公开
    包装结构

    公开(公告)号：US20120205800A1

    公开(公告)日：2012-08-16

    申请号：US13448706

    申请日：2012-04-17

    申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Wen-Hsiung Chang

    发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Wen-Hsiung Chang

    IPC分类号： H01L23/498

    CPC分类号： H01L23/3135 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2225/06548 ,  H01L2924/15311

    摘要： A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.

    摘要翻译： 提出了一种封装结构和封装工艺，其中使用柱状突起来连接上部第二芯片和通过下部第一芯片的硅导通孔，其中第一芯片和第二芯片之间的间隙可以通过调节支柱的高度来控制 颠簸 换句话说，支柱凸块补偿第一芯片和围绕第一芯片的模塑料之间的高度差，以确保柱状凸块与相应的通过硅通孔之间的结合性，并提高工艺产量。 此外，支柱凸块保持第二芯片和模塑料之间的间隙，以使底部填充物适当地填充到第一芯片和第二芯片之间的空间中。

    Package process
    10.
    发明授权
    Package process 有权
    包过程

    公开(公告)号：US08258007B2

    公开(公告)日：2012-09-04

    申请号：US12817396

    申请日：2010-06-17

    申请人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Wen-Hsiung Chang

    发明人： Chi-Chih Shen ,  Jen-Chuan Chen ,  Hui-Shan Chang ,  Wen-Hsiung Chang

    IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L29/40

    CPC分类号： H01L23/3135 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2225/06548 ,  H01L2924/15311

    摘要： A package structure and a package process are proposed in using pillar bumps to connect an upper second chip and through silicon vias of a lower first chip, wherein a gap between the first chip and the second chip can be controlled by adjusting a height of the pillar bumps. In other words, the pillar bumps compensate the height difference between the first chip and a molding compound surrounding the first chip so as to ensure the bondibility between the pillar bumps and the corresponding through silicon vias and improve the process yield. Furthermore, the pillar bumps maintain the gap between the second chip and the molding compound for allowing an underfill being properly filled into the space between the first chip and the second chip.

    摘要翻译： 提出了一种封装结构和封装工艺，其中使用柱状突起来连接上部第二芯片和通过下部第一芯片的硅导通孔，其中第一芯片和第二芯片之间的间隙可以通过调节支柱的高度来控制 颠簸 换句话说，支柱凸块补偿第一芯片和围绕第一芯片的模塑料之间的高度差，以确保柱状凸块与相应的通过硅通孔之间的结合性，并提高工艺产量。 此外，支柱凸块保持第二芯片和模塑料之间的间隙，以使底部填充物适当地填充到第一芯片和第二芯片之间的空间中。