公开(公告)号：US20050164473A1

公开(公告)日：2005-07-28

申请号：US10763305

申请日：2004-01-23

申请人： Jin Liu ,  Dong Sohn ,  Liang Hsia

发明人： Jin Liu ,  Dong Sohn ,  Liang Hsia

IPC分类号： C30B29/52 ,  H01L21/20 ,  H01L29/10 ,  C30B1/00

CPC分类号： C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/0262 ,  H01L29/1054 ,  Y10S438/933

摘要： A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses. In situ growth of an overlying silicon-germanium layer featuring uniform or non-graded germanium content, results in a relaxed silicon-germanium layer with a minimum of dislocations propagating from the underlying graded silicon-germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.

摘要翻译： 已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅 - 锗层的方法。 该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长 的分级第一硅锗层进行。 该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。 具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。 硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

公开(公告)号：US20050164436A1

公开(公告)日：2005-07-28

申请号：US10865433

申请日：2004-06-10

申请人： Jin Liu ,  Dong Sohn ,  Liang Hsia

发明人： Jin Liu ,  Dong Sohn ,  Liang Hsia

IPC分类号： C30B29/52 ,  H01L21/20 ,  H01L29/10 ,  H01L21/338 ,  C30B1/00 ,  H01L21/36

CPC分类号： C30B29/52 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/0262 ,  H01L29/1054

摘要： A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses. In situ growth of an overlying silicon—germanium layer featuring uniform or non—graded germanium content, results in a relaxed silicon—germanium layer with a minimum of dislocations propagating from the underlying graded silicon—germanium layer. In situ growth of a silicon layer results in a tensile strain, low defect density layer to be used for MOSFET device applications.

摘要翻译： 已经开发了形成用于随后的上覆拉伸应变硅层的下层的松弛硅锗层的方法。 该方法的特征在于半导体衬底上的底层第一硅 - 锗层的初始生长，其组成分级以在第一硅 - 锗层和半导体衬底的界面处具有最大的锗含量，锗的含量随着生长 的分级第一硅锗层进行。 该生长序列允许最大的晶格失配和最高级别的穿透位错存在于渐变硅 - 锗层的底部，随着梯度硅 - 锗层的生长进行，晶格失配和穿透位错的大小减小。 具有均匀或非分级锗含量的上覆硅锗层的原位生长导致松弛的硅 - 锗层，其中最小的位错从下面的梯度硅 - 锗层传播。 硅层的原位生长导致用于MOSFET器件应用的拉伸应变，低缺陷密度层。

公开(公告)号：US20060234479A1

公开(公告)日：2006-10-19

申请号：US11107712

申请日：2005-04-15

申请人： Jinping Liu ,  Dong Sohn ,  Liang Hsia

发明人： Jinping Liu ,  Dong Sohn ,  Liang Hsia

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/36 ,  H01L31/20

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/76262 ,  H01L29/78 ,  Y10S438/933

摘要： A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised of silicon oxide and an oxide layer and oxidize the SiGe layer for form a oxide layer. The oxide layer is then removed. An upper semiconductor layer (e.g., Si, SiGe or Ge layer) is epitaxially formed on the SiGe layer. Devices are formed on said an upper semiconductor layer. The buffer layer can be formed by several aspects.

摘要翻译： 一种制造半导体衬底结构的方法，包括以下步骤。 在Si基板上形成缓冲层。 我们在新型缓冲层上形成SiGe层。 缓冲层在其中具有缺陷，使得缓冲层被氧化以形成由氧化硅和氧化物层组成的掩埋隔离层，并氧化SiGe层以形成氧化物层。 然后除去氧化物层。 在SiGe层上外延形成上半导体层（例如Si，SiGe或Ge层）。 器件形成在所述上半导体层上。 缓冲层可以由几个方面形成。

公开(公告)号：US20060160290A1

公开(公告)日：2006-07-20

申请号：US11039428

申请日：2005-01-20

申请人： Yung Chong ,  Dong Sohn ,  Chew-Hue Ang ,  Purakh Vermo ,  Liang Hsia

发明人： Yung Chong ,  Dong Sohn ,  Chew-Hue Ang ,  Purakh Vermo ,  Liang Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823835 ,  H01L21/823842

摘要： An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface. We anneal said metal layer to form fully silicided NMOS gate and fully silicided PMOS gate.

摘要翻译： 描述了在FUSI设备中制造可变功函数门的实施例。 该实施例使用功函数掺杂注入来掺杂多晶硅以实现所需的功函数。 选择性外延生长（SEG）用于在源极/漏极区域上形成硅。 掺杂的多晶硅栅极被完全硅化以形成具有所需功函数的完全硅化栅极。 我们提供具有NMOS区和PMOS区的衬底。 我们在所述衬底上形成栅极介电层和栅极层。 我们进行（栅极Vt）栅极层注入工艺，将诸如P +，As +，B +，BF 2 +，N +，Sb +，In +，C +，Si +，Ge +或Ar +的杂质注入栅极层 NMOS栅极区域和所述PMOS栅极区域中的栅极。 我们在所述栅极层上形成覆盖层。 我们对所述盖层，所述栅极层和所述栅极电介质层进行图案化以形成NMOS栅极和PMOS栅极。 形成间隔物并形成S / D区域。 在所述衬底表面上沉积金属。 我们退火所述金属层以形成完全硅化的NMOS栅极和完全硅化的PMOS栅极。

公开(公告)号：US20060160343A1

公开(公告)日：2006-07-20

申请号：US11039429

申请日：2005-01-20

申请人： Yung Chong ,  Dong Sohn ,  Liang Hsia

发明人： Yung Chong ,  Dong Sohn ,  Liang Hsia

IPC分类号： H01L21/3205

CPC分类号： H01L27/105 ,  H01L21/28512 ,  H01L21/76897 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/7833

摘要： An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening. We perform a bitline contact plug implant to from a doped contact region under the opening. We activate the doped contact region to form an activated doped contact region using a laser irradiation process. The laser irradiation process improves the electrical activation of the doped contact region without interfering with the silicide and S/D regions of the logic devices.

摘要翻译： 使用激光照射激活过程形成用于存储器件的位线接触区域和位线接触插塞的示例性方法。 示例实施例包括：提供具有逻辑区域和SONOS存储器区域的衬底。 在存储区域中形成存储器晶体管，该存储晶体管由存储栅极电介质，存储栅极电极，存储器LDD区域，存储器栅电极的侧壁上的存储器间隔构成。 然后，我们执行“存储单元源线”注入，以在与存储器栅电极相邻的存储器区域中形成存储器源极线。 我们在存储器栅电极和存储器源极线上形成硅化物。 我们在衬底表面上形成一个ILD电介质层。 我们在存储器区域中的存储器漏极上的ILD电介质层中形成接触开口。 我们蚀刻在与存储栅电极相邻的漏极区中的衬底中的开口。 开口第一次暴露存储单元并暴露开口侧壁上的存储器漏极。 我们从开口下方的掺杂接触区域执行位线接触插入注入。 我们激活掺杂接触区域，以使用激光照射工艺形成激活的掺杂接触区域。 激光照射过程改善了掺杂接触区域的电激活，而不会干扰逻辑器件的硅化物和S / D区域。

公开(公告)号：US20060160303A1

公开(公告)日：2006-07-20

申请号：US11039430

申请日：2005-01-20

申请人： Chew-Hoe Ang ,  Dong Sohn ,  Liang Hsia

发明人： Chew-Hoe Ang ,  Dong Sohn ,  Liang Hsia

IPC分类号： H01L21/336

CPC分类号： H01L29/513 ,  H01L21/28282 ,  H01L29/792

摘要： Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.

公开(公告)号：US20060110865A1

公开(公告)日：2006-05-25

申请号：US10992894

申请日：2004-11-19

申请人： Jinping Liu ,  Hwa Koh ,  Dong Sohn ,  Liang Hsia

发明人： Jinping Liu ,  Hwa Koh ,  Dong Sohn ,  Liang Hsia

IPC分类号： H01L21/84 ,  H01L21/31

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

摘要翻译： 公开了一种形成栅介质层的方法。 该方法包括以下步骤。 提供了具有硅区域的衬底，所述硅区域包含要在其上设置栅极电介质的表面。 在表面上形成氧化物。 在氧化物层上形成硅层。 进行氮化处理。 可以进行可选的高温退火步骤。

公开(公告)号：US20060147813A1

公开(公告)日：2006-07-06

申请号：US11028421

申请日：2005-01-03

申请人： Sya Tan ,  Soon Tan ,  Qun Lin ,  Hury Chong ,  Liang Hsia

发明人： Sya Tan ,  Soon Tan ,  Qun Lin ,  Hury Chong ,  Liang Hsia

IPC分类号： G03C5/00 ,  G03F1/00

CPC分类号： G03F1/34

摘要： A chromeless phase shift mask and Method for making and using. The A chromeless phase shift mask is used to pattern contact holes. The chromeless phase shift mask preferably comprises: a first phase shift region and a second phase shfit region; the first region is comprised of a unit cell which is comprised of a rectangular center section and at least three rectangular sections (legs) outwards extending from the rectangular center section. The second region is adjacent to said first region. The interference between the first and second phase shift regions creates a contact hole pattern.

摘要翻译： 无色相移掩模和制造和使用方法。 A无铬相移掩模用于对接触孔进行图案化。 无铬相移掩模优选地包括：第一相移区域和第二相位区域; 第一区域包括由矩形中心部分和从矩形中心部分向外延伸的至少三个矩形部分（腿）的单元电池。 第二区域与所述第一区域相邻。 第一和第二相移区域之间的干涉产生接触孔图案。

公开(公告)号：US20060105533A1

公开(公告)日：2006-05-18

申请号：US10990180

申请日：2004-11-16

申请人： Yung Chong ,  Liang Hsia ,  Chew Ang

发明人： Yung Chong ,  Liang Hsia ,  Chew Ang

IPC分类号： H01L21/8228

CPC分类号： H01L21/823807

摘要： The embodiments provide a structure and a method of manufacturing a semiconductor structure that has a different material in the area where PMOS devices will be formed than in the area where NMOS devices will be formed which is characterized as follows. An embodiment comprises the following steps. A substrate is provided. The substrate has a NMOS area and a PMOS area. We form a NMOS mask over the NMOS area. We form a first semiconductor layer over the PMOS area. We remove the mask. We form a second semiconductor layer over the NMOS area. Then we form an isolation region in the substrate between at least portions of the NMOS and the PMOS areas. We form PMOS devices in the PMOS area and form NMOS devices in the NMOS area.

摘要翻译： 实施例提供一种制造半导体结构的结构和方法，该半导体结构在将要形成PMOS器件的区域中将具有不同于在其上将形成NMOS器件的区域中的材料，其特征如下。 实施例包括以下步骤。 提供基板。 衬底具有NMOS区域和PMOS区域。 我们在NMOS区域上形成NMOS掩模。 我们在PMOS区域上形成第一半导体层。 我们删除面具。 我们在NMOS区域上形成第二个半导体层。 然后，在NMOS和PMOS区域的至少一部分之间，在衬底中形成隔离区。 我们在PMOS区域中形成PMOS器件，并在NMOS区域中形成NMOS器件。

公开(公告)号：US20070134941A1

公开(公告)日：2007-06-14

申请号：US11297485

申请日：2005-12-08

申请人： Huang Liu ,  Bei Zhang ,  Wuping Liu ,  John Sudijono ,  Liang Hsia

发明人： Huang Liu ,  Bei Zhang ,  Wuping Liu ,  John Sudijono ,  Liang Hsia

IPC分类号： H01L21/469

CPC分类号： H01L21/31058 ,  B05D3/068 ,  H01J2237/04735 ,  H01J2237/3156 ,  H01L21/02112 ,  H01L21/02274 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/312 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76834

摘要： An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anode grid between the electron source and the semiconductor structure. We cure the film by exposing the film to an electron beam from the electron source that passes through the anode grid. We control the electron beam by controlling the bias voltage between the anode grid and the semiconductor structure. Another embodiment is a tool for curing a film.

摘要翻译： 示例性实施例是在半导体结构上固化膜的方法。 我们提供由衬底和互连结构组成的半导体结构。 我们提供半导体结构的电影。 我们提供电子源，电子源和半导体结构之间的阳极栅极。 我们通过将膜暴露于电子源通过阳极栅格的电子束来固化膜。 我们通过控制阳极栅极和半导体结构之间的偏置电压来控制电子束。 另一个实施例是用于固化膜的工具。