公开(公告)号：US20050039944A1

公开(公告)日：2005-02-24

申请号：US10850864

申请日：2004-05-21

申请人： Jin-Ho Kim ,  In-Ku Kang ,  Hee-Kook Choi

发明人： Jin-Ho Kim ,  In-Ku Kang ,  Hee-Kook Choi

IPC分类号： H01L23/48 ,  H05K3/24 ,  H05K3/34 ,  H05K1/09 ,  H05K1/02

CPC分类号： H05K3/3452 ,  H01L2224/10 ,  H05K3/243 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0577 ,  H05K2203/058

摘要： In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

摘要翻译： 在一个实施例中，衬垫形成在衬底表面上。 垫与连接图案连接。 在基板上形成第一掩模。 第一掩模具有暴露焊盘的至少一部分和连接图案的一部分的第一开口。 在第一掩模上形成第二掩模。 第二掩模具有暴露焊盘的至少一部分和连接图案的一部分的第二开口。 第一开口的边界面或侧壁不与第二开口的边界面或侧壁共面。 因此，可以防止应力集中在第一开口的边界面上，从而允许应力分散和约束图案裂纹。

公开(公告)号：US07098407B2

公开(公告)日：2006-08-29

申请号：US10850864

申请日：2004-05-21

申请人： Jin-Ho Kim ,  In-Ku Kang ,  Hee-Kook Choi

发明人： Jin-Ho Kim ,  In-Ku Kang ,  Hee-Kook Choi

IPC分类号： H05K1/09

CPC分类号： H05K3/3452 ,  H01L2224/10 ,  H05K3/243 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0577 ,  H05K2203/058

摘要： In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

摘要翻译： 在一个实施例中，衬垫形成在衬底表面上。 垫与连接图案连接。 在基板上形成第一掩模。 第一掩模具有暴露焊盘的至少一部分和连接图案的一部分的第一开口。 在第一掩模上形成第二掩模。 第二掩模具有暴露焊盘的至少一部分和连接图案的一部分的第二开口。 第一开口的边界面或侧壁不与第二开口的边界面或侧壁共面。 因此，可以防止应力集中在第一开口的边界面上，从而允许应力分散和约束图案裂纹。

公开(公告)号：US07030489B2

公开(公告)日：2006-04-18

申请号：US10632700

申请日：2003-07-31

申请人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

发明人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

IPC分类号： H01L23/34

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

摘要翻译： 本文提供具有接合线的多芯片模块（MCM）及其制造方法。 多芯片模块包括基板和顺序层叠的多个芯片。 堆叠在最低芯片上方的至少一个顶部芯片具有覆盖其背面的绝缘膜。 此外，每个堆叠的芯片具有形成在其上表面的周边或边缘上的接合焊盘。 在堆叠的芯片之间插入至少一个绝缘体。 绝缘体暴露底层芯片上的焊盘。 各个芯片的焊盘连接到一组布置在基板上的互连。 堆叠式芯片的这种配置使得由于绝缘膜防止接合线接触顶部芯片的基板而使存储器模块的整体高度减小。

公开(公告)号：US20060125093A1

公开(公告)日：2006-06-15

申请号：US11353509

申请日：2006-02-13

申请人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

发明人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

IPC分类号： H01L23/34

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

公开(公告)号：US20050023674A1

公开(公告)日：2005-02-03

申请号：US10632700

申请日：2003-07-31

申请人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

发明人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

IPC分类号： H01L25/065 ,  H01L23/34

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

摘要翻译： 本文提供具有接合线的多芯片模块（MCM）及其制造方法。 多芯片模块包括基板和顺序层叠的多个芯片。 堆叠在最低芯片上方的至少一个顶部芯片具有覆盖其背面的绝缘膜。 此外，每个堆叠的芯片具有形成在其上表面的周边或边缘上的接合焊盘。 在堆叠的芯片之间插入至少一个绝缘体。 绝缘体暴露底层芯片上的焊盘。 各个芯片的焊盘连接到一组布置在基板上的互连。 堆叠式芯片的这种配置使得由于绝缘膜防止接合线接触顶部芯片的基板而使存储器模块的整体高度减小。

公开(公告)号：US20090130908A1

公开(公告)日：2009-05-21

申请号：US12318386

申请日：2008-12-29

申请人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hae-Hyung Lee ,  Hee-Kook Choi ,  Jin-Yang Lee

发明人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hae-Hyung Lee ,  Hee-Kook Choi ,  Jin-Yang Lee

IPC分类号： H01R24/00

CPC分类号： H01R12/721 ,  H05K3/305 ,  H05K3/306 ,  H05K2201/0133 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1147 ,  H05K2203/304 ,  Y02P70/613

摘要： In a memory module, a gap filler for eliminating an air gap may be formed on an end of a PCB where a tab may be formed. The gap filler may be formed on a surface of a socket receiving the memory module. A grease may be coated on the tab to provide a heat conduction path away from the memory module.

公开(公告)号：US20060151878A1

公开(公告)日：2006-07-13

申请号：US11326192

申请日：2006-01-06

申请人： Se-Young Jeong ,  Nam-Seog Kim ,  Sung-Ki Lee ,  Hee-Kook Choi ,  Ki-Kwon Jeong ,  Tae-Sung Park ,  Yoshikuni Nakadaira ,  Sang-Hyeop Lee ,  Sung-Hwan Kim

发明人： Se-Young Jeong ,  Nam-Seog Kim ,  Sung-Ki Lee ,  Hee-Kook Choi ,  Ki-Kwon Jeong ,  Tae-Sung Park ,  Yoshikuni Nakadaira ,  Sang-Hyeop Lee ,  Sung-Hwan Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/49582 ,  H01L21/4835 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/45099 ,  H01L2924/00

摘要： Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive plating layer. The plating unit and reflow unit may be disposed in a single line with the plating module. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

摘要翻译： 公开了半导体芯片封装装置及其方法的示例性实施例。 包装装置可以包括电镀单元，用于执行导电电镀工艺以在半导体芯片封装的外部端子上形成导电镀层，以及适于熔化导电镀层的回流单元。 电镀单元和回流单元可以与电镀模块一起设置。 因此，可以有效地抑制外部端子的镀层上的晶须的生长，并且能够确保经济效益，降低成本，并且能够批量生产。

公开(公告)号：US07485006B2

公开(公告)日：2009-02-03

申请号：US11093236

申请日：2005-03-30

申请人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hae-Hyung Lee ,  Hee-Kook Choi ,  Jin-Yang Lee

发明人： Sang-Wook Park ,  Joong-Hyun Baek ,  Hae-Hyung Lee ,  Hee-Kook Choi ,  Jin-Yang Lee

IPC分类号： H01R24/00

CPC分类号： H01R12/721 ,  H05K3/305 ,  H05K3/306 ,  H05K2201/0133 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2203/1147 ,  H05K2203/304 ,  Y02P70/613

摘要： In a memory module, a gap filler for eliminating an air gap may be formed on an end of a PCB where a tab may be formed. The gap filler may be formed on a surface of a socket receiving the memory module. A grease may be coated on the tab to provide a heat conduction path away from the memory module.

摘要翻译： 在存储器模块中，可以在PCB的可以形成突片的端部上形成用于消除气隙的间隙填充物。 间隙填料可以形成在接收存储器模块的插座的表面上。 可以在突片上涂覆润滑脂以提供远离存储器模块的热传导路径。

公开(公告)号：US07825495B2

公开(公告)日：2010-11-02

申请号：US12007920

申请日：2008-01-17

申请人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

发明人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

IPC分类号： H01L29/06

CPC分类号： H01L23/49816 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

摘要翻译： 半导体芯片结构可以包括半导体芯片，第一绝缘层和再分配层。 第一绝缘层可以形成在半导体芯片上。 第一绝缘层可以具有形成在第一绝缘层的上表面部分处的至少一个第一凹槽。 此外，所述至少一个第一凹槽可以具有大于上宽度的上宽度和下宽度。 再分布层可以部分地形成在第一绝缘层上。 再分配层可以具有形成在再分布层的下表面部分上的至少一个第一突起。 第一突起可以具有小于上宽度的上宽度和下宽度。 第一突起可插入至少一个第一凹槽中。

公开(公告)号：US20080174025A1

公开(公告)日：2008-07-24

申请号：US12007920

申请日：2008-01-17

申请人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

发明人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

IPC分类号： H01L23/488 ,  H01L21/4763

CPC分类号： H01L23/49816 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

摘要翻译： 半导体芯片结构可以包括半导体芯片，第一绝缘层和再分配层。 第一绝缘层可以形成在半导体芯片上。 第一绝缘层可以具有形成在第一绝缘层的上表面部分处的至少一个第一凹槽。 此外，所述至少一个第一凹槽可以具有大于上宽度的上宽度和下宽度。 再分布层可以部分地形成在第一绝缘层上。 再分配层可以具有形成在再分布层的下表面部分上的至少一个第一突起。 第一突起可以具有小于上宽度的上宽度和下宽度。 第一突起可插入至少一个第一凹槽中。