公开(公告)号：US20060151878A1

公开(公告)日：2006-07-13

申请号：US11326192

申请日：2006-01-06

申请人： Se-Young Jeong ,  Nam-Seog Kim ,  Sung-Ki Lee ,  Hee-Kook Choi ,  Ki-Kwon Jeong ,  Tae-Sung Park ,  Yoshikuni Nakadaira ,  Sang-Hyeop Lee ,  Sung-Hwan Kim

发明人： Se-Young Jeong ,  Nam-Seog Kim ,  Sung-Ki Lee ,  Hee-Kook Choi ,  Ki-Kwon Jeong ,  Tae-Sung Park ,  Yoshikuni Nakadaira ,  Sang-Hyeop Lee ,  Sung-Hwan Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/49582 ,  H01L21/4835 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/45099 ,  H01L2924/00

摘要： Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive plating layer. The plating unit and reflow unit may be disposed in a single line with the plating module. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

摘要翻译： 公开了半导体芯片封装装置及其方法的示例性实施例。 包装装置可以包括电镀单元，用于执行导电电镀工艺以在半导体芯片封装的外部端子上形成导电镀层，以及适于熔化导电镀层的回流单元。 电镀单元和回流单元可以与电镀模块一起设置。 因此，可以有效地抑制外部端子的镀层上的晶须的生长，并且能够确保经济效益，降低成本，并且能够批量生产。

公开(公告)号：US20060202332A1

公开(公告)日：2006-09-14

申请号：US11418010

申请日：2006-05-05

申请人： Se-Young Jeong ,  Gi-Young Sohn ,  Ki-Kwon Jeong ,  Hyeon Hwang

发明人： Se-Young Jeong ,  Gi-Young Sohn ,  Ki-Kwon Jeong ,  Hyeon Hwang

IPC分类号： H01L23/48

CPC分类号： H01L21/4835 ,  H01L23/49582 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2224/45099 ,  H01L2924/00

摘要： Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus includes a plating unit that is disposed in a direction to form a conductive plating layer on external terminals of the semiconductor chip package; and a reflow unit that is disposed with the plating unit to melt the conductive plating layer. The packaging apparatus may further include a rinsing unit that is disposed with the plating unit to clean and cool the conductive plating layer. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

摘要翻译： 公开了半导体芯片封装装置及其方法的示例性实施例。 包装装置包括镀敷单元，该镀覆单元沿着在半导体芯片封装的外部端子上形成导电镀层的方向设置; 以及与所述电镀单元配置以熔化所述导电性镀层的回流单元。 包装装置还可以包括与镀覆单元一起设置以清洁和冷却导电镀层的冲洗单元。 因此，可以有效地抑制外部端子的镀层上的晶须的生长，并且能够确保经济效益，降低成本，并且能够批量生产。

公开(公告)号：US20090141275A1

公开(公告)日：2009-06-04

申请号：US12327066

申请日：2008-12-03

申请人： Il-Young HAN ,  Mitsuo Umemoto ,  Ki-Kwon Jeong ,  Young-shin Choi

发明人： Il-Young HAN ,  Mitsuo Umemoto ,  Ki-Kwon Jeong ,  Young-shin Choi

IPC分类号： G01B11/00 ,  B32B37/12

CPC分类号： G01B11/272 ,  B32B37/06 ,  B32B37/1018 ,  B32B38/1841 ,  B32B41/00 ,  B32B2310/028 ,  B32B2457/08

摘要： A method of inspecting the alignment of a second structure with respect to a first structure, including emitting light from a first plane of a first structure to a second plane of a second structure in a first direction perpendicular to the first plane of the first structure, the first plane and the second plane facing each other. The incident light can be reflected from the second plane toward the first plane in a second direction parallel with the first direction. The position of the reflected light can be detected to inspect the alignment of the second structure with respect to the first structure.

摘要翻译： 一种检查第二结构相对于第一结构的对准的方法，包括在垂直于第一结构的第一平面的第一方向上将光从第一结构的第一平面发射到第二结构的第二平面， 第一平面和第二平面彼此面对。 入射光可以在与第一方向平行的第二方向上从第二平面朝向第一平面反射。 可以检测反射光的位置，以检查第二结构相对于第一结构的对准。

公开(公告)号：US07494845B2

公开(公告)日：2009-02-24

申请号：US11144213

申请日：2005-06-02

申请人： Hyeon Hwang ,  Ki-Kwon Jeong

发明人： Hyeon Hwang ,  Ki-Kwon Jeong

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L23/481 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.

摘要翻译： 形成薄晶片堆叠的方法提供了晶片级堆叠，以便在晶片被锯切之后分开分离的芯片的方法中大大减少处理时间。 刚性平面晶片支撑构件在其薄或其厚度减小和在随后的晶片处理期间稳定和平坦化每个晶片。 将薄的晶片堆叠并且通过向支撑构件和薄晶片之间的可扩张的粘合剂层施加热或紫外线（UV）光来去除外部支撑构件。 然后可以进一步处理和封装堆叠的晶片，而不会出现薄片翘曲，开裂或断裂。 还公开了根据本发明方法制造的晶片级封装。

公开(公告)号：US20050282374A1

公开(公告)日：2005-12-22

申请号：US11144213

申请日：2005-06-02

申请人： Hyeon Hwang ,  Ki-Kwon Jeong

发明人： Hyeon Hwang ,  Ki-Kwon Jeong

IPC分类号： H01L23/12 ,  H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L21/68 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L21/6835 ,  H01L23/481 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

摘要： A method of forming a stack of thin wafers provides a wafer level stack to greatly reduce process time compared to a method where individually separated chips are stacked after a wafer is sawed. A rigid planar wafer support member stabilizes and planarizes each wafer while it is thin or its thickness is reduced and during subsequent wafer processing. Thinned wafers are stacked and the external support members are removed by applying heat or ultraviolet (UV) light to an expandable adhesive layer between the support members and the thin wafers. The stacked wafers then can be further processed and packaged without thin-wafer warping, cracking or breaking. A wafer level package made in accordance with the invented method also is disclosed.

摘要翻译： 形成薄晶片堆叠的方法提供了晶片级堆叠，以便在晶片被锯切之后分开分离的芯片的方法中大大减少处理时间。 刚性平面晶片支撑构件在其薄或其厚度减小和在随后的晶片处理期间稳定和平坦化每个晶片。 将薄的晶片堆叠并且通过向支撑构件和薄晶片之间的可扩张的粘合剂层施加热或紫外线（UV）光来去除外部支撑构件。 然后可以进一步处理和封装堆叠的晶片，而不会出现薄片翘曲，开裂或断裂。 还公开了根据本发明方法制造的晶片级封装。

公开(公告)号：US07479455B2

公开(公告)日：2009-01-20

申请号：US11157905

申请日：2005-06-22

申请人： Ki-Kwon Jeong ,  Hyeon Hwang

发明人： Ki-Kwon Jeong ,  Hyeon Hwang

IPC分类号： H01L21/302

CPC分类号： H01L21/6836 ,  H01L21/304 ,  H01L21/30625 ,  H01L2221/68327

摘要： A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

摘要翻译： 一种方法可包括使用粘合剂将第一支撑板安装在晶片的有效表面上。 晶片背表面的一部分可能被重叠。 可以使用粘合剂将第二支撑板安装在晶片的背面上。 第一支撑板可以从晶片的有效表面移除。 可以在活性表面上设置导电凸块。 重叠过程可以包括第一研磨工艺，第二研磨工艺和抛光工艺。 第一和第二支撑板可以由固体材料制成。 粘合剂可以是紫外线固化粘合剂或热固化粘合剂。

公开(公告)号：US20060177954A1

公开(公告)日：2006-08-10

申请号：US11397824

申请日：2006-04-03

申请人： Ki-Kwon Jeong ,  Dong-Kuk Kim

发明人： Ki-Kwon Jeong ,  Dong-Kuk Kim

IPC分类号： H01L21/00 ,  H01L21/50

CPC分类号： H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68395 ,  Y10T29/49121 ,  Y10T29/5313 ,  Y10T29/53187 ,  Y10T29/53261

摘要： A dicing tape attaching unit that can attach both a pre-cut dicing tape and a general dicing tape to a wafer in a semiconductor package assembling process, and an in-line system used in a semiconductor package process including the dicing tape attaching unit are provided. The dicing tape attaching unit supplies one of the pre-cut dicing tape and the general dicing tape and attaches it to a wafer according to the direction of rotation of a tape loader. Accordingly, without an additional pre-cut dicing tape attaching unit, either of the pre-cut dicing tape and the general dicing tape can be attached to the back side of the wafer by one and the same unit.

摘要翻译： 在半导体封装组装工序中，可以将预切割的切割带和一般的切割带与晶片连接的切割胶带安装单元，以及在包括切割胶带安装部的半导体封装工序中使用的在线系统 。 切割胶带安装单元提供预切割切割带和一般切割带中的一个，并根据带式装载机的旋转方向将其附接到晶片。 因此，没有附加的预切割切割胶带安装单元，预切割切割带和一般切割带中的任一个可以通过同一单元附接到晶片的背面。

公开(公告)号：US20060166462A1

公开(公告)日：2006-07-27

申请号：US11157905

申请日：2005-06-22

申请人： Ki-Kwon Jeong ,  Hyeon Hwang

发明人： Ki-Kwon Jeong ,  Hyeon Hwang

IPC分类号： H01L21/461

CPC分类号： H01L21/6836 ,  H01L21/304 ,  H01L21/30625 ,  H01L2221/68327

摘要： A method may involve mounting a first supporting plate on an active surface of a wafer using an adhesive. A portion of the back surface of the wafer may be backlapped. A second supporting plate may be mounted on the back surface of the wafer using an adhesive. The first supporting plate may be removed from the active surface of the wafer. Conductive bumps may be provided on the active surface. A backlapping process may include a first grinding process, a second grinding process, and a polishing process. The first and the second supporting plates may be fabricated from a solid material. The adhesive may be an ultraviolet cure adhesive or a thermal cure adhesive.

公开(公告)号：US07129118B2

公开(公告)日：2006-10-31

申请号：US10621576

申请日：2003-07-18

申请人： Cheol-Joon Yoo ,  Ki-Kwon Jeong

发明人： Cheol-Joon Yoo ,  Ki-Kwon Jeong

IPC分类号： H01L21/58 ,  B23P19/00

CPC分类号： H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/68354 ,  H01L2224/83192 ,  Y10S156/942 ,  Y10T29/53178 ,  Y10T29/53191 ,  Y10T156/1978

摘要： A method of utilizing a removable protective tape to protect the active surfaces of semiconductor wafer and the individual semiconductor chips during semiconductor packaging processes is provided along with several configurations of apparatuses that may be used in such a method for removing protective tape portions from individual semiconductor chips during the assembly process.

摘要翻译： 在半导体封装工艺期间利用可移除的保护带来保护半导体晶片和各个半导体芯片的有源表面的方法与可用于从各个半导体芯片去除保护带部分的方法中使用的几种设备一起提供 在装配过程中。

公开(公告)号：US20050153522A1

公开(公告)日：2005-07-14

申请号：US10944002

申请日：2004-09-20

申请人： Hyeon Hwang ,  Dong-Kuk Kim ,  Ki-Kwon Jeong

发明人： Hyeon Hwang ,  Dong-Kuk Kim ,  Ki-Kwon Jeong

IPC分类号： H01L21/60 ,  H01L21/00 ,  H01L21/44 ,  H01L21/48 ,  H01L21/58 ,  H01L21/68 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065

CPC分类号： H01L24/27 ,  H01L21/67132 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/29 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/83001 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2224/83 ,  H01L2924/00

摘要： Provided is a method by which differently-sized chips may be stacked at the wafer level. The wafer level chip stack method utilizes first and second wafer assemblies that support first and second wafers on adhesive tapes. One or both of the supported wafers may be sawed or otherwise divided to obtain separate first and second chips that remain fixed to respective first ring frames. The first and second wafer assemblies may then be positioned and aligned so that a back surface of the second wafer faces an active surface of the first wafer. Each of the second chips may then be bonded to a corresponding first chip to form a chip stack using an adhesive layer. The chip stacks may then be detached from the wafer assemblies and attached to a substrate.

摘要翻译： 提供了可以在晶片级堆叠不同大小的芯片的方法。 晶片级芯片堆叠方法利用在胶带上支撑第一和第二晶片的第一和第二晶片组件。 支撑的晶片中的一个或两个可以锯切或以其他方式分割，以获得保持固定到相应的第一环形框架的分离的第一和第二芯片。 然后可以将第一和第二晶片组件定位和对准，使得第二晶片的后表面面向第一晶片的有效表面。 然后可以将每个第二芯片结合到相应的第一芯片以使用粘合剂层形成芯片堆叠。 然后可以将芯片堆叠从晶片组件分离并附接到衬底。