公开(公告)号：US07825495B2

公开(公告)日：2010-11-02

申请号：US12007920

申请日：2008-01-17

申请人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

发明人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

IPC分类号： H01L29/06

CPC分类号： H01L23/49816 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

摘要翻译： 半导体芯片结构可以包括半导体芯片，第一绝缘层和再分配层。 第一绝缘层可以形成在半导体芯片上。 第一绝缘层可以具有形成在第一绝缘层的上表面部分处的至少一个第一凹槽。 此外，所述至少一个第一凹槽可以具有大于上宽度的上宽度和下宽度。 再分布层可以部分地形成在第一绝缘层上。 再分配层可以具有形成在再分布层的下表面部分上的至少一个第一突起。 第一突起可以具有小于上宽度的上宽度和下宽度。 第一突起可插入至少一个第一凹槽中。

公开(公告)号：US20080174025A1

公开(公告)日：2008-07-24

申请号：US12007920

申请日：2008-01-17

申请人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

发明人： Seung-Kwan Ryu ,  Hee-Kook Choi ,  Sung-Min Sim ,  Dong-Hyeon Jang

IPC分类号： H01L23/488 ,  H01L21/4763

CPC分类号： H01L23/49816 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

摘要翻译： 半导体芯片结构可以包括半导体芯片，第一绝缘层和再分配层。 第一绝缘层可以形成在半导体芯片上。 第一绝缘层可以具有形成在第一绝缘层的上表面部分处的至少一个第一凹槽。 此外，所述至少一个第一凹槽可以具有大于上宽度的上宽度和下宽度。 再分布层可以部分地形成在第一绝缘层上。 再分配层可以具有形成在再分布层的下表面部分上的至少一个第一突起。 第一突起可以具有小于上宽度的上宽度和下宽度。 第一突起可插入至少一个第一凹槽中。

公开(公告)号：US07205660B2

公开(公告)日：2007-04-17

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US07312143B2

公开(公告)日：2007-12-25

申请号：US11717691

申请日：2007-03-14

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

摘要翻译： 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20060214293A1

公开(公告)日：2006-09-28

申请号：US11186763

申请日：2005-07-22

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

摘要翻译： 晶片级芯片级封装可以具有设置在焊料凸块和凸起焊盘之间的间隙。 间隙可以填充气体。 制造晶片级芯片级封装的方法可以包括形成具有第一开口的再分配线，形成具有包括底切部分的第二开口的种子金属层，以及使用第一和第二开口形成间隙。

公开(公告)号：US20070176290A1

公开(公告)日：2007-08-02

申请号：US11717691

申请日：2007-03-14

申请人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

发明人： Myeong-Soon Park ,  Hyun-Soo Chung ,  In-Young Lee ,  Jae-Sik Chung ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Young-Hee Song ,  Seung-Kwan Ryu

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02165 ,  H01L2224/02335 ,  H01L2224/02351 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/10125 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13018 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599

摘要： A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

公开(公告)号：US20070069320A1

公开(公告)日：2007-03-29

申请号：US11486041

申请日：2006-07-14

申请人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

发明人： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

IPC分类号： H01L31/00

CPC分类号： H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/114 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/013

摘要： A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.

摘要翻译： 布线结构可以包括垫，导电图案和绝缘光致抗蚀剂结构。 垫可以设置在主体上并电连接到主体的电路单元。 导电图案可以设置在主体上并且可以电连接到垫。 绝缘光致抗蚀剂结构可以设置在导电图案的表面上。 绝缘光致抗蚀剂结构可以具有接触孔，导电图案可以通过该接触孔部分地暴露。 绝缘光致抗蚀剂结构可以通过在导电层上提供感光性光致抗蚀剂膜，并通过两个照相工艺对感光性光刻胶膜进行图案化来制造。

公开(公告)号：US08039937B2

公开(公告)日：2011-10-18

申请号：US12432003

申请日：2009-04-29

申请人： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC分类号： H01L23/02

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

摘要： Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

摘要翻译： 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。

公开(公告)号：US10186500B2

公开(公告)日：2019-01-22

申请号：US15357741

申请日：2016-11-21

申请人： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

发明人： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC分类号： H01L25/10 ,  H01L25/00

摘要： A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：US07544538B2

公开(公告)日：2009-06-09

申请号：US11775120

申请日：2007-07-09

申请人： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

发明人： Hyun-Soo Chung ,  Seung-Kwan Ryu ,  Ju-Il Choi ,  Dong-Ho Lee ,  Seong-Deok Hwang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/76898 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/036 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/01028 ,  H01L2224/03

摘要： Provided are methods of fabricating semiconductor chips, semiconductor chips formed by the methods, and chip-stack packages having the semiconductor chips. One embodiment specifies a method that includes patterning a scribe line region of a semiconductor substrate to form a semiconductor strut spaced apart from edges of a chip region of the semiconductor substrate.

摘要翻译： 提供制造半导体芯片的方法，通过该方法形成的半导体芯片和具有半导体芯片的芯片堆叠封装。 一个实施例规定了一种方法，其包括图案化半导体衬底的划线区域以形成与半导体衬底的芯片区域的边缘间隔开的半导体支柱。