公开(公告)号：US4502207A

公开(公告)日：1985-03-05

申请号：US562212

申请日：1983-12-16

申请人： Jiro Ohshima ,  Masahiro Abe ,  Yutaka Koshino

发明人： Jiro Ohshima ,  Masahiro Abe ,  Yutaka Koshino

IPC分类号： H01L21/3215 ,  H01L23/532 ,  H01L21/28

CPC分类号： H01L23/53219 ,  H01L21/3215 ,  H01L2924/0002 ,  Y10T428/12528

摘要： A wiring material of a semiconductor device, which comprises aluminum as a major component and at least a surface layer of the wiring layer is alloyed with boron and silicon. A method for forming a wiring material of a semiconductor device, which comprises the steps of: forming a wiring pattern comprising aluminum as a major component on a semiconductor element; and ion-implanting one of boron and a mixture of boron and silicon in the wiring pattern and alloying at least a surface layer of the wiring pattern to form an alloy layer containing aluminum, boron and silicon.

摘要翻译： 包含铝作为主要成分的半导体器件的布线材料和布线层的至少表面层与硼和硅合金化。 一种形成半导体器件布线材料的方法，包括以下步骤：在半导体元件上形成包含铝作为主要成分的布线图案; 并在布线图案中离子注入硼和硼与硅的混合物中的一种，并在布线图案的至少表面层合金化，形成含有铝，硼和硅的合金层。

公开(公告)号：US4404736A

公开(公告)日：1983-09-20

申请号：US319411

申请日：1981-11-09

申请人： Yutaka Koshino ,  Takashi Ajima ,  Jiro Ohshima ,  Masahiro Abe

发明人： Yutaka Koshino ,  Takashi Ajima ,  Jiro Ohshima ,  Masahiro Abe

IPC分类号： H01L21/316 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L23/3171 ,  H01L21/316 ,  H01L23/291 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/3511 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/159 ,  Y10S438/928

摘要： A method for manufacturing a semiconductor device of mesa type comprises forming mesa recesses of predetermined depth around an element in the surface of a semiconductor body, forming on the back of semiconductor body a film for lessening the concentration of stress, filling glass powder into mesa recesses, and sintering glass powder to form glass insulators. According to the method of the present invention, cracks can be prevented from being caused in the semiconductor body and glass insulators formed in mesa recesses.

摘要翻译： 一种台面型半导体器件的制造方法包括在半导体本体的表面的元件周围形成预定深度的台面凹部，在半导体本体的背面形成用于减小应力集中的膜，将玻璃粉末填充到台面凹部 ，并烧结玻璃粉末以形成玻璃绝缘体。 根据本发明的方法，可以防止在形成在台面凹部中的半导体本体和玻璃绝缘体中产生裂纹。

公开(公告)号：US4515642A

公开(公告)日：1985-05-07

申请号：US525484

申请日：1983-08-22

申请人： Takashi Ajima ,  Jiro Ohshima ,  Yutaka Koshino

发明人： Takashi Ajima ,  Jiro Ohshima ,  Yutaka Koshino

IPC分类号： H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L21/316

CPC分类号： H01L21/02178 ,  H01L21/02263 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/3162

摘要： In a method of producing a semiconductor device, an alumina layer is formed directly on a principal surface of a silicon substrate; aluminum and silicon are ion-implanted through the alumina layer into said substrate; and the substrate is thereafter annealed. The ion-implanted silicon yields better crystalline structure and increases the solid solubility limit of aluminum.

摘要翻译： 在制造半导体器件的方法中，氧化铝层直接形成在硅衬底的主表面上; 铝和硅通过氧化铝层离子注入到所述衬底中; 然后退火基板。 离子注入的硅产生更好的晶体结构并增加铝的固溶度极限。

公开(公告)号：US4479830A

公开(公告)日：1984-10-30

申请号：US462201

申请日：1983-01-31

申请人： Yutaka Koshino ,  Jiro Ohshima ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Yutaka Koshino ,  Jiro Ohshima ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/2652 ,  H01L2223/54453 ,  H01L2924/0002

摘要： A method for manufacturing a semiconductor device is shown which includes a step of ion implanting an impurity into an impurity-region formation region of a semiconductor substrate. Before or after the ion implantation step, silicon ions are implanted in a dose of 1.times.10.sup.13 to 1.times.10.sup.15 /cm.sup.2 into the impurity-region formation region and then the silicon ions so implanted are subjected to an activation treatment to form an epitaxial grown protrusion on the surface of the substrate. The protrusion is used as an alignment mark in the subsequent mask alignment step for photolithography.

摘要翻译： 示出了制造半导体器件的方法，其包括将杂质离子注入到半导体衬底的杂质区形成区域中的步骤。 在离子注入步骤之前或之后，将硅离子以1×10 13至1×10 15 / cm 2的剂量注入杂质区形成区域，然后将如此注入的硅离子进行活化处理，以在表面上形成外延生长突起 的基底。 在随后的用于光刻的掩模对准步骤中，该突起用作对准标记。

公开(公告)号：US4415372A

公开(公告)日：1983-11-15

申请号：US313332

申请日：1981-10-20

申请人： Yutaka Koshino ,  Toshio Yonezawa ,  Takashi Ajima ,  Jiro Ohshima

发明人： Yutaka Koshino ,  Toshio Yonezawa ,  Takashi Ajima ,  Jiro Ohshima

IPC分类号： H01L21/263 ,  H01L21/265 ,  H01L21/324

CPC分类号： H01L21/324 ,  H01L21/2636 ,  H01L21/26513 ,  Y10S148/046

摘要： The invention provides a method for fabricating a semiconductor device which comprises the steps of ion-implanting an impurity into a monocrystalline semiconductor substrate; irradiating the region into which the impurity ions have been implanted with an accelerated electron beam under the conditions that the acceleration voltage is 20 to 200 KeV, and the current is 0.01 to 1 mA and the exposure dose is 10.sup.20 to 10.sup.15 /cm.sup.2 ; and carrying out annealing to form a semiconductor region of one conductivity type. According to the present invention, a semiconductor device can be fabricated which has fewer lattice defects and in which the lifetime of the carriers is long.

摘要翻译： 本发明提供一种制造半导体器件的方法，该方法包括以下步骤：将杂质离子注入到单晶半导体衬底中; 在加速电压为20〜200KeV，电流为0.01〜1mA，曝光量为1020〜1015 / cm2的条件下，用加速电子束照射杂质离子注入的区域; 并进行退火以形成一种导电类型的半导体区域。 根据本发明，可以制造具有更少的晶格缺陷并且其中载体的寿命长的半导体器件。

公开(公告)号：US4780426A

公开(公告)日：1988-10-25

申请号：US101026

申请日：1987-09-24

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Jiro Ohshima

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Jiro Ohshima

IPC分类号： H01L21/033 ,  H01L21/22 ,  H01L21/225 ,  H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/73 ,  H01L21/385 ,  H01L21/425

CPC分类号： H01L29/6625 ,  H01L21/033 ,  H01L21/22 ,  H01L21/2253 ,  H01L29/0615 ,  H01L29/1004

摘要： A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.

摘要翻译： 在n型硅衬底的主表面上形成第一氧化硅膜。 在第一氧化硅膜上形成氮化硅膜。 选择性地蚀刻第一氧化硅膜和氮化硅膜以形成开口。 使用第一氧化硅膜和氮化硅膜作为掩模将硼离子注入到硅衬底中。 在由开口暴露的硅衬底上形成第二氧化硅膜。 使用氮化硅膜作为掩模将镓离子注入到第二氧化硅膜中。 硼和镓离子同时扩散到硅衬底中。 在这种情况下，硅衬底中镓的扩散速率高于硅衬底中的硼的扩散速率，并且硅氧化膜中镓的扩散速率高于硅衬底中的扩散速率。 因此，在衬底中形成p型第二层，以自对准的方式包围p +型第一层。

公开(公告)号：US4426234A

公开(公告)日：1984-01-17

申请号：US327190

申请日：1981-12-03

申请人： Jiro Ohshima ,  Yutaka Koshino ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Jiro Ohshima ,  Yutaka Koshino ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/3115 ,  H01L21/425 ,  H01L21/74

CPC分类号： H01L21/31155 ,  H01L21/2255 ,  H01L21/265

摘要： The invention discloses a method for fabricating a semiconductor device comprising the steps of: forming, on an entire surface of a semiconductor substrate of one conductivity type, a first thin film of a diffusion coefficient greater than a diffusion coefficient of the substrate; forming, on an entire surface of the first thin film, a second thin film having a diffusion coefficient smaller than the diffusion coefficient of the first thin film; ion-implanting an impurity through the second thin film into the first thin film to form an impurity region, said impurity having a conductivity type opposite to the conductivity type of the substrate; and effecting annealing to set a junction depth of the impurity region to a predetermined value. According to the method of the invention, an impurity region having a desired sheet resistivity and a desired diffusion depth can be formed in the semiconductor substrate with excellent reproducibility and control. The formation of the lattice defect can be prevented and the carrier life time can be improved. Gallium is preferably used as the impurity according to the invention.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：在一个导电类型的半导体衬底的整个表面上形成大于衬底扩散系数的扩散系数的第一薄膜; 在所述第一薄膜的整个表面上形成扩散系数小于所述第一薄膜的扩散系数的第二薄膜; 将杂质通过第二薄膜离子注入到第一薄膜中以形成杂质区，所述杂质具有与衬底的导电类型相反的导电类型; 并进行退火以将杂质区域的结深度设定为预定值。 根据本发明的方法，可以在半导体衬底中形成具有期望的电阻率和期望的扩散深度的杂质区，具有优异的再现性和控制性。 可以防止晶格缺陷的形成，并且可以提高载体寿命。 优选使用镓作为本发明的杂质。

公开(公告)号：US5637894A

公开(公告)日：1997-06-10

申请号：US544834

申请日：1995-10-18

申请人： Masako Hori ,  Masaaki Ogawa ,  Hidenori Shibata ,  Yoshiyuki Shioyama ,  Yutaka Koshino

发明人： Masako Hori ,  Masaaki Ogawa ,  Hidenori Shibata ,  Yoshiyuki Shioyama ,  Yutaka Koshino

IPC分类号： G09F9/00 ,  H01L21/339 ,  H01L27/148 ,  H01L29/762

CPC分类号： H01L27/14831

摘要： A charge coupled device, together with a method for manufacturing the device, is provided which can eliminate a conventional problem, that is, the remaining of a light-receiving film at a great step area and a consequent lowering of a sensitivity resulting from the shutting-off of a portion of incident light. In the charge coupled device, insulating areas are formed in substantially strip-like array on a silicon substrate. Respective transfer electrodes are formed on a gate insulating film on a semiconductor substrate with an insulating areas interposed. The respective phase transfer electrodes are electrically separated by the insulating area. By doing so, the respective phase transfer electrodes can be formed on the same plane without leaving a greater step. This can achieve a thinned light shielding film.

摘要翻译： 提供了电荷耦合器件，以及用于制造器件的方法，其可以消除常规问题，即，在大步进区域处的光接收膜的剩余部分以及由此导致的灵敏度的降低 一部分入射光。 在电荷耦合器件中，绝缘区域在硅衬底上形成为大致带状的阵列。 各个传输电极形成在半导体衬底上的绝缘膜上的绝缘膜上。 各个相转移电极被绝缘区域电隔离。 通过这样做，各个相转移电极可以形成在同一平面上，而不会留下更大的台阶。 这可以实现减薄的遮光膜。

公开(公告)号：US4968932A

公开(公告)日：1990-11-06

申请号：US251601

申请日：1988-09-30

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Seiji Yasuda

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Seiji Yasuda

IPC分类号： G01R19/00 ,  G01R31/26 ,  G01R31/265 ,  G01R31/311 ,  H01L21/66

CPC分类号： G01R31/2656 ,  G01R31/2608 ,  G01R31/311

摘要： An evaluation method for a semiconductor device includes the steps of applying a reverse bias voltage between an N-type substrate formed in a surface of the semiconductor device and a P-type region formed in a surface of the N-type substrate to form a depletion layer along the junction therebetween, scanning the surface of the semiconductor device is one direction with a light beam to cause an optical beam induced current to be flow across the junction, and measuring the OBIC intensity profile on a scanning line extending across the depletion layer in the surfaces of the N-type substrate and P-type region. In the method, the light beam has a wavelength whose penetration length is smaller than the depth or thickness of the P-type region, the OBIC intensity profile is integrated over a range corresponding to the depletion layer, and the integrated value is normalized by the reverse bias voltage to determine the surface potential distribution of the semiconductor device.

公开(公告)号：US4566174A

公开(公告)日：1986-01-28

申请号：US545545

申请日：1983-10-26

申请人： Seiji Yasuda ,  Yutaka Koshino ,  Toshio Yonezawa

发明人： Seiji Yasuda ,  Yutaka Koshino ,  Toshio Yonezawa

IPC分类号： H01L27/082 ,  H01L21/20 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8224 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/74 ,  H01L21/8224 ,  H01L21/82285 ,  H01L21/8238 ,  H01L27/0826 ,  Y10S148/05

摘要： A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the grooves, and an epitaxial layer of the opposite conductivity type is further grown to a depth enough to fill a deeper one of the grooves, followed by the step of etching the entire surface to expose the surface of said semiconductor substrate and to leave in each groove an epitaxial layer of mutually different conductivity type and having the same depth and width. A semiconductor device as manufactured by the above method.

摘要翻译： 一种制造半导体器件的方法，其中在半导体衬底的表面中形成具有不同深度的一对沟槽，一个导电类型的外延层生长到足以填充较浅的一个沟槽的深度，并且外延 相反导电类型的层进一步生长到足以填充更深的一个沟槽的深度，接着是蚀刻整个表面以暴露所述半导体衬底的表面并且在每个沟槽中留下相互的外延层的步骤 不同的导电类型，具有相同的深度和宽度。 通过上述方法制造的半导体器件。