公开(公告)号：US4968932A

公开(公告)日：1990-11-06

申请号：US251601

申请日：1988-09-30

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Seiji Yasuda

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Seiji Yasuda

IPC分类号： G01R19/00 ,  G01R31/26 ,  G01R31/265 ,  G01R31/311 ,  H01L21/66

CPC分类号： G01R31/2656 ,  G01R31/2608 ,  G01R31/311

摘要： An evaluation method for a semiconductor device includes the steps of applying a reverse bias voltage between an N-type substrate formed in a surface of the semiconductor device and a P-type region formed in a surface of the N-type substrate to form a depletion layer along the junction therebetween, scanning the surface of the semiconductor device is one direction with a light beam to cause an optical beam induced current to be flow across the junction, and measuring the OBIC intensity profile on a scanning line extending across the depletion layer in the surfaces of the N-type substrate and P-type region. In the method, the light beam has a wavelength whose penetration length is smaller than the depth or thickness of the P-type region, the OBIC intensity profile is integrated over a range corresponding to the depletion layer, and the integrated value is normalized by the reverse bias voltage to determine the surface potential distribution of the semiconductor device.

公开(公告)号：US4984052A

公开(公告)日：1991-01-08

申请号：US418587

申请日：1989-10-10

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L21/763 ,  H01L27/12

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286 ,  Y10S257/914

摘要： A bonded substrate comprises a first semiconductor substrate in which a plurality of semiconductor elements are formed, a second semiconductor substrate adhered to the first semiconductor substrate so as to support it by means of an insulating layer interposed therebetween, a first semi-insulating polysilicon layer interposed between the first semiconductor substrate and the insulating layer, and a second semi-insulating polysilicon layer interposed between the insulating layer and the second semiconductor substrate. The semi-insulating polysilicon layers serve to reduce the voltage applied to the insulating layer and to prevent the insulating layer from being etched.

摘要翻译： 键合衬底包括其中形成有多个半导体元件的第一半导体衬底，第二半导体衬底，其粘附到第一半导体衬底，以便通过插入其间的绝缘层来支撑它;第一半绝缘多晶硅层， 在第一半导体衬底和绝缘层之间，以及插入在绝缘层和第二半导体衬底之间的第二半绝缘多晶硅层。 半绝缘多晶硅层用于降低施加到绝缘层的电压并防止绝缘层被蚀刻。

公开(公告)号：US5126817A

公开(公告)日：1992-06-30

申请号：US596286

申请日：1990-10-12

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Kenji Yamawaki

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Kenji Yamawaki

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/763 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286

摘要： A dielectrically isolated structure for use in an SOI-type semiconductor device according to the present invention comprises a substrate having an element-forming region formed therein on a first insulating film, the region being made of a first material, at least one trench formed in the element-forming region and extending to the first insulating film, second insulating films formed on side walls of the trench, and a film made of a second material, and embedded in only an upper portion of the trench such that a bottom portion of the trench is hollow.

摘要翻译： 根据本发明的用于SOI型半导体器件的介电隔离结构包括在第一绝缘膜上形成有元件形成区域的衬底，该区域由第一材料制成，至少一个沟槽形成在 元件形成区域并延伸到第一绝缘膜，形成在沟槽的侧壁上的第二绝缘膜和由第二材料制成的膜，并且仅嵌入在沟槽的上部中，使得底部部分 沟是空心的

公开(公告)号：US5084408A

公开(公告)日：1992-01-28

申请号：US596294

申请日：1990-10-15

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76283 ,  H01L21/76286 ,  Y10S438/978

摘要： For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.

公开(公告)号：US5029324A

公开(公告)日：1991-07-02

申请号：US512013

申请日：1990-04-16

申请人： Akihiko Osawa ,  Yutaka Koshino ,  Yoshiro Baba

发明人： Akihiko Osawa ,  Yutaka Koshino ,  Yoshiro Baba

IPC分类号： H01L21/60 ,  H01L21/314 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/408 ,  H01L23/29 ,  H01L23/53271 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05686 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/3025

摘要： A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.

公开(公告)号：US5031021A

公开(公告)日：1991-07-09

申请号：US905958

申请日：1986-09-11

申请人： Yoshiro Baba ,  Kazuo Tsuru ,  Tatsuo Akiyama ,  Yutaka Koshino

发明人： Yoshiro Baba ,  Kazuo Tsuru ,  Tatsuo Akiyama ,  Yutaka Koshino

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/04 ,  H01L29/06 ,  H01L29/40 ,  H01L29/732

CPC分类号： H01L29/405 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/408

摘要： There is disclosed a power transistor comprising a semiconductor substrate having a PN junction exposed on a major surface of the semiconductor substrate, and a semiinsulative polysilicon film formed on the major surface, the polysilicon film covering the PN junction, the polysilicon film containing at least one of carbon, oxygen, and nitrogen, and the polysilicon film having a thickness of about 3000 .ANG..

摘要翻译： 公开了一种功率晶体管，其包括具有在该半导体衬底的主表面上露出的PN结的半导体衬底和形成在该主表面上的半绝缘性多晶硅膜，该多晶硅膜覆盖该PN结，该多晶硅膜含有至少一个 的碳，氧和氮，以及多晶硅膜的厚度约为3000纳米。

公开(公告)号：US5086332A

公开(公告)日：1992-02-04

申请号：US415400

申请日：1989-09-27

申请人： Akio Nakagawa ,  Kiminori Watanabe ,  Yutaka Koshino ,  Yoshihiro Yamaguchi ,  Yoshiro Baba

发明人： Akio Nakagawa ,  Kiminori Watanabe ,  Yutaka Koshino ,  Yoshihiro Yamaguchi ,  Yoshiro Baba

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/405 ,  H01L29/0615 ,  H01L29/408 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/41758

摘要： A planar semiconductor device having a high breakdown voltage includes a semiconductor layer of a first conductivity type and a first semiconductor region of a second conductivity type selectively formed, together with the semiconductor layer, in the surface of the semiconductor layer forming a pn junction. The first semiconductor region is formed to have an impurity concentration higher than that of the semiconductor layer and therefore a resistivity higher than that of the semiconductor layer. A second semiconductor region of the second conductivity type having an impurity concentration lower than that of the first semiconductor region, is formed around and in contact with the first semiconductor region and together with the semiconductor layer constitutes a pn junction. A high resistance film is formed at least over the first semiconductor region and the second semiconductor region. A voltage is applied across the high resistance film to create a uniform electric field in the high resistance film.

摘要翻译： 具有高击穿电压的平面半导体器件包括在形成pn结的半导体层的表面中选择性地与半导体层一起形成第一导电类型的半导体层和第二导电类型的第一半导体区域。 第一半导体区域形成为具有比半导体层高的杂质浓度，因此电阻率高于半导体层的电阻率。 具有低于第一半导体区域的杂质浓度的第二导电类型的第二半导体区域形成在第一半导体区域周围并与第一半导体区域接触，并与半导体层一起构成pn结。 至少在第一半导体区域和第二半导体区域上形成高电阻膜。 在高电阻膜上施加电压以在高电阻膜中产生均匀的电场。

公开(公告)号：US4780426A

公开(公告)日：1988-10-25

申请号：US101026

申请日：1987-09-24

申请人： Yutaka Koshino ,  Yoshiro Baba ,  Jiro Ohshima

发明人： Yutaka Koshino ,  Yoshiro Baba ,  Jiro Ohshima

IPC分类号： H01L21/033 ,  H01L21/22 ,  H01L21/225 ,  H01L21/331 ,  H01L29/06 ,  H01L29/10 ,  H01L29/73 ,  H01L21/385 ,  H01L21/425

CPC分类号： H01L29/6625 ,  H01L21/033 ,  H01L21/22 ,  H01L21/2253 ,  H01L29/0615 ,  H01L29/1004

摘要： A first silicon oxide film is formed on the major surface of an n-type silicon substrate. A silicon nitride film is formed on the first silicon oxide film. The first silicon oxide film and the silicon nitride film are selectively etched to form an opening. Boron ions are implanted into the silicon substrate using the first silicon oxide film and the silicon nitride film as a mask. A second silicon oxide film is formed on the silicon substrate exposed by the opening. Gallium ions are implanted into the second silicon oxide film using the silicon nitride film as a mask. Boron and gallium ions are simultaneously diffused in the silicon substrate. In this case, a diffusion rate of gallium in the silicon substrate is higher than that of boron in the silicon substrate, and the diffusion rate of gallium in the silicon oxide film is higher than that in the silicon substrate. Therefore, a p-type second layer is formed in the substrate to surround a p.sup.+ -type first layer in a self-aligned manner.

摘要翻译： 在n型硅衬底的主表面上形成第一氧化硅膜。 在第一氧化硅膜上形成氮化硅膜。 选择性地蚀刻第一氧化硅膜和氮化硅膜以形成开口。 使用第一氧化硅膜和氮化硅膜作为掩模将硼离子注入到硅衬底中。 在由开口暴露的硅衬底上形成第二氧化硅膜。 使用氮化硅膜作为掩模将镓离子注入到第二氧化硅膜中。 硼和镓离子同时扩散到硅衬底中。 在这种情况下，硅衬底中镓的扩散速率高于硅衬底中的硼的扩散速率，并且硅氧化膜中镓的扩散速率高于硅衬底中的扩散速率。 因此，在衬底中形成p型第二层，以自对准的方式包围p +型第一层。

公开(公告)号：US4710794A

公开(公告)日：1987-12-01

申请号：US828536

申请日：1986-02-12

申请人： Yutaka Koshino ,  Tatsuo Akiyama ,  Yoshiro Baba

发明人： Yutaka Koshino ,  Tatsuo Akiyama ,  Yoshiro Baba

IPC分类号： H01L29/06 ,  H01L21/18 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/07 ,  H01L27/082 ,  H01L27/12 ,  H01L25/04

CPC分类号： H01L21/8249 ,  H01L21/187 ,  H01L21/76264 ,  H01L21/76297 ,  H01L21/764 ,  H01L21/8222 ,  H01L27/0716 ,  H01L27/0825 ,  H01L21/76286 ,  H01L21/76289

摘要： Disclosed is a composite semiconductor device, comprising a composite substrate consisting of first and second semiconductor substrates, one surface of each of which is mirror-polished, so that the mirror-polished surfaces are bonded together. The first semiconductor substrate has a space adjacent to the bonding interface, and an annular groove which communicates with the space from a surface of the first semiconductor substrate opposite the bonding interface, the annular groove being formed in a portion of the first semiconductor substrate corresponding to a peripheral edge portion of the space thereof, at least one pillar projecting through the space to the bonding interface from a surface, which is exposed to the space, of a first portion of the first semiconductor substrate which is defined by the space and the annular groove, a first insulating layer, formed in the annular groove, for electrically isolating the first portion from a second portion of the first semiconductor substrate adjacent thereto, a second insulating layer, formed on the pillar or a bonding interface between the pillar and the second semiconductor substrate, for electrically isolating the first portion from the second semiconductor substrate, a first functional element formed in the first portion, and a second functional element formed in the second portion.

摘要翻译： 公开了一种复合半导体器件，其包括由第一和第二半导体衬底组成的复合衬底，每个半导体衬底的一个表面被镜面抛光，使得镜面抛光表面被接合在一起。 所述第一半导体衬底具有与所述接合界面相邻的空间，以及与所述第一半导体衬底的与所述接合界面相对的表面与所述空间连通的环形槽，所述环形槽形成在所述第一半导体衬底的对应于 其空间的外围边缘部分，至少一个从所述空间向所述接合界面突出的第一半导体衬底的第一部分暴露于所述空间的表面的至少一个柱，所述第一部分由所述空间和环形 槽，形成在环形槽中的第一绝缘层，用于将第一部分与与其相邻的第一半导体衬底的第二部分电隔离;形成在柱上的第二绝缘层或柱与第二绝缘层之间的接合界面 半导体衬底，用于将第一部分与第二半导体衬底电隔离，第一 形成在第一部分中的功能元件和形成在第二部分中的第二功能元件。

公开(公告)号：US4566174A

公开(公告)日：1986-01-28

申请号：US545545

申请日：1983-10-26

申请人： Seiji Yasuda ,  Yutaka Koshino ,  Toshio Yonezawa

发明人： Seiji Yasuda ,  Yutaka Koshino ,  Toshio Yonezawa

IPC分类号： H01L27/082 ,  H01L21/20 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8224 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/74 ,  H01L21/8224 ,  H01L21/82285 ,  H01L21/8238 ,  H01L27/0826 ,  Y10S148/05

摘要： A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the grooves, and an epitaxial layer of the opposite conductivity type is further grown to a depth enough to fill a deeper one of the grooves, followed by the step of etching the entire surface to expose the surface of said semiconductor substrate and to leave in each groove an epitaxial layer of mutually different conductivity type and having the same depth and width. A semiconductor device as manufactured by the above method.

摘要翻译： 一种制造半导体器件的方法，其中在半导体衬底的表面中形成具有不同深度的一对沟槽，一个导电类型的外延层生长到足以填充较浅的一个沟槽的深度，并且外延 相反导电类型的层进一步生长到足以填充更深的一个沟槽的深度，接着是蚀刻整个表面以暴露所述半导体衬底的表面并且在每个沟槽中留下相互的外延层的步骤 不同的导电类型，具有相同的深度和宽度。 通过上述方法制造的半导体器件。