利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.019 秒)

    On-chip thermal sensing circuit
    1.
    发明授权
    On-chip thermal sensing circuit 失效
    片上热感测电路

    公开(公告)号：US06914764B2

    公开(公告)日：2005-07-05

    申请号：US10195173

    申请日：2002-07-11

    申请人： Joachim Gerhard Clabes ,  Ronald Nick Kalla ,  Stephen Douglas Weitzel

    发明人： Joachim Gerhard Clabes ,  Ronald Nick Kalla ,  Stephen Douglas Weitzel

    IPC分类号： G01K7/20 ,  H03K3/0231 ,  H02H5/04

    CPC分类号： G01K7/203 ,  H03K3/0231

    摘要： An on-chip thermal sensing circuit is disclosed. The thermal sensing circuit including a detection circuit located on an integrated circuit (IC) for detecting a local temperature of the IC. The output of the thermal sensor has a frequency that is directly related to the local temperature. The detection circuit has an associated time constant that is used to produce the frequency.

    摘要翻译： 公开了片上热感测电路。 热感测电路包括位于用于检测IC的局部温度的集成电路（IC）上的检测电路。 热传感器的输出具有与局部温度直接相关的频率。 检测电路具有用于产生频率的相关时间常数。

    Performance throttling for temperature reduction in a microprocessor
    2.
    发明授权
    Performance throttling for temperature reduction in a microprocessor 失效
    微处理器降温性能节流

    公开(公告)号：US07051221B2

    公开(公告)日：2006-05-23

    申请号：US10425399

    申请日：2003-04-28

    申请人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

    发明人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Balaram Sinharoy

    IPC分类号： G06F1/32

    CPC分类号： G06F9/3017 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D50/20

    摘要： A microprocessor includes a functional block having dynamic power savings circuitry, a functional block control circuit, and a thermal control unit. The functional block control circuits are capable of altering performance characteristics of their associated functional blocks automatically upon detecting an over temperature condition. The thermal control unit receives an over-temperature signal indicating a processor temperature exceeding a threshold and invokes the one or more of the functional block control units in response to the signal. The functional block control units respond to signals from the thermal control unit by reducing processor activity, slowing processor performance, or both. The reduced activity that results causes the dynamic power saving circuitry to engage. The functional block control units can throttle performance by numerous means including reducing the exploitable parallelism within the processor, suspending out-of-order execution, reducing effective resource size, and the like.

    摘要翻译： 微处理器包括具有动态功率节省电路的功能块，功能块控制电路和热控制单元。 功能块控制电路能够在检测到过温度条件时自动改变其相关功能块的性能特性。 热控制单元接收指示处理器温度超过阈值的过温度信号，并响应于该信号调用一个或多个功能块控制单元。 功能块控制单元通过减少处理器活动，降低处理器性能或两者来响应来自热控制单元的信号。 导致动态省电电路参与的活动减少。 功能块控制单元可以通过多种方式来抑制性能，包括减少处理器内可利用的并行性，暂停无序执行，减少有效的资源大小等。

    Thermally aware integrated circuit
    3.
    发明授权
    Thermally aware integrated circuit 有权
    热感知集成电路

    公开(公告)号：US07657772B2

    公开(公告)日：2010-02-02

    申请号：US10366437

    申请日：2003-02-13

    申请人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Paul David Muench ,  Lawrence Joseph Powell

    发明人： Joachim Gerhard Clabes ,  Michael Stephen Floyd ,  Paul David Muench ,  Lawrence Joseph Powell

    IPC分类号： G06F1/04 ,  G06F1/14

    CPC分类号： H01L27/0248 ,  G01K7/425

    摘要： An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

    摘要翻译： 一种具有温度敏感电路（TSC）的集成电路，用于产生指示TSC附近的衬底温度的信号。 集成电路具有被配置为从至少一个TSC接收TSC信号并且将TSC信号转换成指示集成电路的温度的信号的电路。 热控制电路将集成电路温度与阈值进行比较，并在温度超过阈值时产生校正动作信号。 校正动作信号被提供给校正动作电路，优选地被配置为修改IC的操作以降低接近相应TSC的IC温度。

    Design techniques for analyzing integrated circuit device characteristics
    4.
    发明授权
    Design techniques for analyzing integrated circuit device characteristics 失效
    分析集成电路器件特性的设计技术

    公开(公告)号：US06951002B2

    公开(公告)日：2005-09-27

    申请号：US10455164

    申请日：2003-06-05

    申请人： Joachim Gerhard Clabes ,  Anand Haridass ,  Michael F. Wang

    发明人： Joachim Gerhard Clabes ,  Anand Haridass ,  Michael F. Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5036 ,  G06F17/5068

    摘要： An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.

    摘要翻译： 一种改进的集成电路设备物理设计和布局的方法和系统。 将集成电路器件的物理布局最佳地存储在数据库中，以提供集成电路器件特性的改进的分析能力。 该方法和系统使用此优化数据库评估芯片给定平面图上的功能块和去耦单元之间的本地交互，以减少内存和处理器利用率。 通过使用dI / dt和电容估计来预测局部噪声。 识别出最高噪声的区域，并通过调整相邻去耦单元的布局及其属性来采取平面图缓解措施。 在几个迭代循环中，实现了总芯片给定平面图的近似最优解。

    Enhanced debug scheme for LBIST
    5.
    发明授权
    Enhanced debug scheme for LBIST 失效
    LBIST增强的调试方案

    公开(公告)号：US06901546B2

    公开(公告)日：2005-05-31

    申请号：US09876753

    申请日：2001-06-07

    申请人： Sam Gat-Shang Chu ,  Joachim Gerhard Clabes ,  Michael Normand Goulet ,  Johnny J. Leblanc ,  James Douglas Warnock

    发明人： Sam Gat-Shang Chu ,  Joachim Gerhard Clabes ,  Michael Normand Goulet ,  Johnny J. Leblanc ,  James Douglas Warnock

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/3187 ,  G06F11/27 ,  G01R31/28 ,  G06R11/00

    CPC分类号： G01R31/3187 ,  G01R31/31705 ,  G01R31/318502 ,  G06F11/27

    摘要： A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.

    摘要翻译： 用于微处理器芯片中的故障测试的装置提供具有第一参考标识的LBIST电路。 进一步提供加载单元，用于接收和输出一组屏蔽数据。 还提供连接到加载单元的文件单元用于接收掩蔽数据。 还提供连接到文件单元的掩蔽单元，用于基于来自文件单元的掩蔽数据和来自芯片中的扫描串的扫描数据来生成第二参考签名。 并且，还提供连接到屏蔽单元的输出的签名逻辑，用于压缩第二参考签名并将压缩的第二参考签名输入到LBIST电路，其中压缩的第二参考签名替换第一参考签名。

    Computer chip heat responsive method and apparatus
    6.
    发明授权
    Computer chip heat responsive method and apparatus 有权
    计算机芯片热响应方法和装置

    公开(公告)号：US06934658B2

    公开(公告)日：2005-08-23

    申请号：US10401410

    申请日：2003-03-27

    申请人： Joachim Gerhard Clabes ,  Lawrence Joseph Powell, Jr. ,  Daniel Lawrence Stasiak ,  Michael Fan Wang

    发明人： Joachim Gerhard Clabes ,  Lawrence Joseph Powell, Jr. ,  Daniel Lawrence Stasiak ,  Michael Fan Wang

    IPC分类号： G06F1/00 ,  G01K3/00 ,  G06F1/20 ,  H01L21/822 ,  H01L27/04 ,  G01K1/08 ,  G01K17/00 ,  H01L31/00

    CPC分类号： G06F1/206 ,  G01K3/005 ,  G06F1/324 ,  Y02D10/126

    摘要： Disclosed is an apparatus incorporating hardware based logic and a predetermined default list of software affecting responses to be taken in connection with temperatures sensed by thermal sensors checking the temperature of portions of computer logic. At the time application software is loaded, the software can modify the default response list. The list of responses to be taken and the over temperature conditions at which they are to be activated are stored in hardware directly accessible by hardware based thermal sensor monitoring logic for direct control of the hardware. The control can alter conditions such as clock frequency, stopping use of application software, interrupting OS functionality, removing power from components and so forth.

    摘要翻译： 公开了一种装置，其包含基于硬件的逻辑和预期的默认的软件列表，该缺省软件影响与由热传感器检测到的温度有关的响应而被采用，所述热传感器检测计算机逻辑部分的温度。 在应用软件加载的时候，软件可以修改默认的响应列表。 要采用的响应列表和它们被激活的过热条件存储在硬件直接可访问的硬件的热传感器监控逻辑中，以直接控制硬件。 该控件可以改变诸如时钟频率，停止使用应用软件，中断OS功能，从组件中移除电力等等的状况。

    Method, system, and computer program product for improving wireability near dense clock nets
    8.
    发明授权
    Method, system, and computer program product for improving wireability near dense clock nets 失效
    方法，系统和计算机程序产品，用于提高密集时钟网络附近的有线性

    公开(公告)号：US06728944B2

    公开(公告)日：2004-04-27

    申请号：US09998049

    申请日：2001-11-29

    申请人： Joachim Gerhard Clabes ,  Thomas Edward Rosser

    发明人： Joachim Gerhard Clabes ,  Thomas Edward Rosser

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Logic blocks that are a particular type are identified. During placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized.

    摘要翻译： 公开了一种用于在包括多个逻辑块的逻辑设计中改善靠近时钟网络的可线性的方法，系统和计算机产品。 每个逻辑块具有实际的物理大小。 识别出特定类型的逻辑块。 在放置逻辑块期间，每个识别的逻辑块的明显物理大小被用作所识别的逻辑块的物理大小。 表观物理尺寸大于实际物理尺寸。 在路由期间，利用每个识别的逻辑块的实际物理大小。

    Method of power consumption reduction in clocked circuits
    10.
    发明授权
    Method of power consumption reduction in clocked circuits 失效
    时钟电路功耗降低的方法

    公开(公告)号：US06922818B2

    公开(公告)日：2005-07-26

    申请号：US09833429

    申请日：2001-04-12

    申请人： Sam Gat-Shang Chu ,  Joachim Gerhard Clabes ,  Michael Normand Goulet ,  Thomas Edward Rosser ,  James Douglas Warnock

    发明人： Sam Gat-Shang Chu ,  Joachim Gerhard Clabes ,  Michael Normand Goulet ,  Thomas Edward Rosser ,  James Douglas Warnock

    IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F17/50 ,  H03K3/037

    CPC分类号： G06F17/505

    摘要： A method and apparatus for reducing power consumption of a clocked circuit containing a plurality of latches is provided. A first latch, within the plurality of latches, is located which has more than a predetermined slack. The possibility of substituting an available second latch, that requires less power to operate, is then determined, subject to the constraint that the slack after substitution should still be positive, although it may be less than the predetermined number mentioned above. Where such a possibility is determined to exist, the first latch is then replaced with the available second latch.

    摘要翻译： 提供了一种用于降低包含多个锁存器的时钟电路的功耗的方法和装置。 在多个闩锁内的第一闩锁被定位，其具有多于预定的松弛。 然后确定替代可用的第二锁存器的可能性，其需要更少的功率来操作，但是受到替代后的松弛仍然是正的限制，尽管它可能小于上述预定数量。 在确定存在这种可能性的情况下，然后用可用的第二锁存器替换第一锁存器。