公开(公告)号：US08679975B2

公开(公告)日：2014-03-25

申请号：US13004599

申请日：2011-01-11

申请人： Jochen Reinmuth ,  Barbara Will ,  Heribert Weber

发明人： Jochen Reinmuth ,  Barbara Will ,  Heribert Weber

IPC分类号： H01L21/60

CPC分类号： H01L21/3081 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C1/00404 ,  B81C1/00626 ,  H01L21/0334 ,  H01L21/76229

摘要： A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.

摘要翻译： 描述了一种用于在半导体部件，特别是微机电或电半导体部件中形成至少一个凹部的方法，其具有以下步骤：将至少一个掩模施加到半导体部件，形成至少一个具有至少一个或多个 在要形成的凹部上的掩模中的格子孔，形成作为蚀刻速率和/或要形成的凹部的尺寸的函数的格子孔或格子孔; 在网格下面形成凹陷。

公开(公告)号：US20110169125A1

公开(公告)日：2011-07-14

申请号：US13004599

申请日：2011-01-11

申请人： Jochen REINMUTH ,  Barbara Will ,  Heribert Weber

发明人： Jochen REINMUTH ,  Barbara Will ,  Heribert Weber

IPC分类号： H01L29/06 ,  H01L21/60

CPC分类号： H01L21/3081 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81B2203/033 ,  B81C1/00404 ,  B81C1/00626 ,  H01L21/0334 ,  H01L21/76229

摘要： A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.

摘要翻译： 描述了一种用于在半导体部件，特别是微机电或电半导体部件中形成至少一个凹部的方法，其具有以下步骤：将至少一个掩模施加到半导体部件，形成至少一个具有至少一个或多个 在要形成的凹部上的掩模中的格子孔，形成作为蚀刻速率和/或要形成的凹部的尺寸的函数的格子孔或格子孔; 在网格下面形成凹陷。

公开(公告)号：US09153523B2

公开(公告)日：2015-10-06

申请号：US14307108

申请日：2014-06-17

申请人： Heribert Weber ,  Hartmut Kueppers ,  Jochen Reinmuth ,  Neil Davies ,  Jens Frey

发明人： Heribert Weber ,  Hartmut Kueppers ,  Jochen Reinmuth ,  Neil Davies ,  Jens Frey

IPC分类号： H01L23/52 ,  H01L23/48 ,  B81C3/00

CPC分类号： H01L23/481 ,  B81C1/00238 ,  B81C3/001 ,  B81C2203/0109 ,  B81C2203/0792 ,  G01C19/5783 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an ASIC element, vias are integrated into the CMOS processing of an ASIC substrate. The ASIC element includes an active front side in which the circuit functions are implemented. The at least one via is intended to establish an electrical connection between the active front side and the rear side of the element. The front side of the via is defined by at least one front-side trench which is completely filled, and the rear side is defined by at least one rear-side trench which is not completely filled. The rear-side trench opens into the filled front-side trench.

摘要翻译： 在ASIC元件中，通孔被集成到ASIC基板的CMOS处理中。 ASIC元件包括其中实现电路功能的主动正面。 该至少一个通孔旨在在元件的主动前侧和后侧之间建立电连接。 通孔的前侧由完全填充的至少一个前侧沟槽限定，并且后侧由未完全填充的至少一个后侧沟槽限定。 后侧沟槽穿过填充的前侧沟槽。

公开(公告)号：US20140117472A1

公开(公告)日：2014-05-01

申请号：US14061887

申请日：2013-10-24

申请人： Julian Gonska ,  Jochen Reinmuth ,  Kathrin Gutsche ,  Jens Frey ,  Heribert Weber

发明人： Julian Gonska ,  Jochen Reinmuth ,  Kathrin Gutsche ,  Jens Frey ,  Heribert Weber

IPC分类号： B81B3/00 ,  B81C1/00

CPC分类号： B81C1/00285 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2207/096 ,  B81C2203/0118 ,  B81C2203/035

摘要： A micromechanical component includes a first space in which a first sensor is situated and a second space in which a second sensor is situated, different pressures prevailing in the first and second spaces, one of the two spaces extending via a third space to a first lattice structure which is situated in an edge region of the component and is essentially hermetically sealed.

摘要翻译： 微机械部件包括第一传感器所在的第一空间和第二传感器所在的第二空间，在第一和第二空间中存在不同的压力，两个空间中的一个通过第三空间延伸到第一格子 结构位于组件的边缘区域中，并且基本上被气密地密封。

公开(公告)号：US09035432B2

公开(公告)日：2015-05-19

申请号：US13915353

申请日：2013-06-11

申请人： Jochen Reinmuth ,  Heribert Weber ,  Timo Schary ,  Yvonne Bergmann

发明人： Jochen Reinmuth ,  Heribert Weber ,  Timo Schary ,  Yvonne Bergmann

IPC分类号： H01L29/40 ,  H01L31/00 ,  H01L23/495 ,  H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  H01L21/7682 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for producing a component having a semiconductor substrate with through-hole plating is provided, the through-plating being surrounded by a recess, and the semiconductor substrate having a first layer on one side, which covers the recess on the first side. The semiconductor substrate has a second layer on a second side, which covers the recess on the second side, and the through-hole plating is surrounded by a ring structure which is produced from the semiconductor substrate. The recess surrounding the ring structure is produced in the same process step or at the same time as the recess for the through-hole plating.

摘要翻译： 提供了具有带通孔电镀的半导体基板的部件的制造方法，所述贯通电镀被凹部包围，所述半导体基板在一侧具有覆盖所述第一侧的所述凹部的第一层。 半导体衬底在第二侧上具有覆盖第二侧的凹部的第二层，并且通孔电镀被由半导体衬底产生的环形结构包围。 围绕环结构的凹部在相同的工艺步骤中或与用于通孔电镀的凹槽同时产生。

公开(公告)号：US08659099B2

公开(公告)日：2014-02-25

申请号：US13586576

申请日：2012-08-15

申请人： Jochen Reinmuth ,  Heribert Weber

发明人： Jochen Reinmuth ,  Heribert Weber

IPC分类号： H01L29/84

CPC分类号： G01P15/0802 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2203/0136 ,  G01C19/5783

摘要： A method for manufacturing a micromechanical structure includes: forming a first insulation layer above a substrate; forming a first micromechanical functional layer on the first insulation layer; forming multiple first trenches in the first micromechanical functional layer, which trenches extend as far as the first insulation layer; forming a second insulation layer on the first micromechanical functional layer, which second insulation layer fills up the first trenches; forming etch accesses in the second insulation layer, which etch accesses locally expose the first micromechanical functional layer; and etching the first micromechanical functional layer through the etch accesses, the filled first trenches and the first insulation layer acting as an etch stop.

摘要翻译： 一种制造微机械结构的方法包括：在基板上形成第一绝缘层; 在所述第一绝缘层上形成第一微机械功能层; 在所述第一微机械功能层中形成多个第一沟槽，所述沟槽延伸到所述第一绝缘层; 在所述第一微机械功能层上形成第二绝缘层，所述第二绝缘层填充所述第一沟槽; 在所述第二绝缘层中形成蚀刻访问，所述蚀刻访问局部暴露所述第一微机械功能层; 并且通过蚀刻访问蚀刻第一微机械功能层，填充的第一沟槽和用作蚀刻停止层的第一绝缘层。

公开(公告)号：US08607447B2

公开(公告)日：2013-12-17

申请号：US13004427

申请日：2011-01-11

申请人： Jochen Reinmuth ,  Heribert Weber

发明人： Jochen Reinmuth ,  Heribert Weber

IPC分类号： H01L23/488 ,  H01L21/768

CPC分类号： B81B7/0006 ,  B81B2207/096 ,  H01L21/743 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/1461 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4922 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for providing and connecting a first contact area to at least one second contact area on a substrate, in particular in the case of a semiconductor component, which includes providing at least one insulation layer on the substrate, forming an opening in the at least one insulation layer over at least one insulation trench of a first contact area, applying at least one metal layer to the insulation layer, forming the first and second contact areas in the at least one metal layer and at least one printed conductor between the two contact areas, and forming the insulation trench.

摘要翻译： 一种用于将第一接触区域提供并连接到衬底上的至少一个第二接触区域的方法，特别是在半导体部件的情况下，其包括在所述衬底上提供至少一个绝缘层，至少在所述衬底上形成开口 在第一接触区域的至少一个绝缘沟槽上的一个绝缘层，将至少一个金属层施加到所述绝缘层，在所述至少一个金属层中形成所述第一和第二接触区域，以及在所述两个接触件之间形成至少一个印刷导体 区域，并形成绝缘沟槽。

公开(公告)号：US20130043548A1

公开(公告)日：2013-02-21

申请号：US13586576

申请日：2012-08-15

申请人： Jochen Reinmuth ,  Heribert Weber

发明人： Jochen Reinmuth ,  Heribert Weber

IPC分类号： H01L29/84 ,  H01L21/02

CPC分类号： G01P15/0802 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2203/0136 ,  G01C19/5783

摘要： A method for manufacturing a micromechanical structure includes: forming a first insulation layer above a substrate; forming a first micromechanical functional layer on the first insulation layer; forming multiple first trenches in the first micromechanical functional layer, which trenches extend as far as the first insulation layer; forming a second insulation layer on the first micromechanical functional layer, which second insulation layer fills up the first trenches; forming etch accesses in the second insulation layer, which etch accesses locally expose the first micromechanical functional layer; and etching the first micromechanical functional layer through the etch accesses, the filled first trenches and the first insulation layer acting as an etch stop.

摘要翻译： 一种制造微机械结构的方法包括：在基板上形成第一绝缘层; 在所述第一绝缘层上形成第一微机械功能层; 在所述第一微机械功能层中形成多个第一沟槽，所述沟槽延伸到所述第一绝缘层; 在所述第一微机械功能层上形成第二绝缘层，所述第二绝缘层填充所述第一沟槽; 在所述第二绝缘层中形成蚀刻访问，所述蚀刻访问局部暴露所述第一微机械功能层; 并且通过蚀刻访问蚀刻第一微机械功能层，填充的第一沟槽和用作蚀刻停止层的第一绝缘层。

公开(公告)号：US08759136B2

公开(公告)日：2014-06-24

申请号：US13431399

申请日：2012-03-27

申请人： Hubert Benzel ,  Heribert Weber

发明人： Hubert Benzel ,  Heribert Weber

IPC分类号： H01L29/84

CPC分类号： G01L9/0042 ,  G01L9/0045 ,  G01L9/0054 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/084

摘要： An electrically insulating sheathing for a piezoresistor and a semiconductor material are provided such that the piezoresistor is able to be used in the high temperature range, e.g., for measurements at higher ambient temperatures than 200° C. A doped resistance area is initially laterally delineated by at least one circumferential essentially vertical trench and is undercut by etching over the entire area. An electrically insulating layer is then created on the wall of the trench and the undercut area, so that the resistance area is electrically insulated from the adjacent semiconductor material by the electrically insulating layer.

摘要翻译： 提供了用于压电电阻器和半导体材料的电绝缘护套，使得压敏电阻器能够在高温范围内使用，例如用于在高于200℃的较高环境温度下测量。掺杂电阻区域最初由 至少一个周向基本上垂直的沟槽，并且通过在整个区域上的蚀刻而被切削。 然后在沟槽的壁和底切区域上形成电绝缘层，使得电阻区域通过电绝缘层与相邻的半导体材料电绝缘。

公开(公告)号：US20120038030A1

公开(公告)日：2012-02-16

申请号：US13198651

申请日：2011-08-04

申请人： Jens Frey ,  Heribert Weber ,  Eckhard Graf ,  Roman Schlosser

发明人： Jens Frey ,  Heribert Weber ,  Eckhard Graf ,  Roman Schlosser

IPC分类号： H01L29/41 ,  H01L21/762 ,  H01L29/06

CPC分类号： H01L21/76898 ,  H01L21/02118 ,  H01L21/02318 ,  H01L21/486 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to the predetermined surface of the wafer; heating the wafer at a first temperature; driving out gas bubbles enclosed in the filling material by heating the wafer under vacuum at a second temperature which is equal to or higher than the first temperature; and curing the filling material by heating the wafer at a third temperature which is higher than the second temperature. Furthermore, also described is a blind hole filled using such a method and general 3D cavities as well as a wafer having insulation trenches of a silicon via filled using such a method.

摘要翻译： 描述了一种用于在晶片中填充空腔的方法，空腔朝向晶片的预定表面开放，包括以下步骤：将漆状填充材料施加到晶片的预定表面; 在第一温度下加热晶片; 通过在等于或高于第一温度的第二温度下在真空下加热晶片来驱除封闭在填充材料中的气泡; 以及通过在高于第二温度的第三温度下加热晶片来固化填充材料。 此外，还描述了使用这种方法和一般3D空腔填充的盲孔以及具有使用这种方法填充的硅通孔的绝缘沟槽的晶片。