公开(公告)号：US08283766B2

公开(公告)日：2012-10-09

申请号：US12874446

申请日：2010-09-02

申请人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

发明人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/495 ,  H01L23/02

CPC分类号： H01L25/0657 ,  G02B6/43 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16135 ,  H01L2224/16151 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81141 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/819 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/1015 ,  H01L2924/10155 ,  H01L2924/151

摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

摘要翻译： 描述了斜坡堆叠芯片封装。 该芯片封装包括在水平方向彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的高带宽斜坡部件被电气和机械耦合到暴露的焊盘。 例如，斜坡部件可以使用：焊料，微弹簧和/或各向异性导电膜耦合到半导体管芯。 此外，每个半导体管芯包括静态弯曲部，使得每个半导体管芯的端部段平行于该方向，并机械耦合到斜坡部件。 这些端段可以促进芯片和斜坡部件之间的信号的高带宽通信，例如通过接近通信。

公开(公告)号：US08373280B2

公开(公告)日：2013-02-12

申请号：US12873945

申请日：2010-09-01

申请人： John A. Harada ,  Robert J. Drost ,  David C. Douglas

发明人： John A. Harada ,  Robert J. Drost ,  David C. Douglas

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/42 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102

摘要： An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.

摘要翻译： 描述了使用组装部件组装芯片封装的组装部件和技术。 该芯片封装包括沿垂直方向布置成堆叠的一组半导体管芯，它们在水平方向上彼此偏移，以限定在垂直堆叠的一侧上阶梯状梯度。 此外，可以使用组件部件组装芯片封装。 特别地，组件部件可以包括具有另一阶梯式台阶的壳体。 该另外的阶梯式平台可以包括在水平方向上彼此偏移的垂直方向的一系列步骤。 此外，壳体可以被配置为与该组半导体管芯配合，使得该组半导体管芯沿着垂直方向布置在堆叠中。 例如，其他阶梯式露台大概可以是阶梯式露台的镜像。

公开(公告)号：US08290319B2

公开(公告)日：2012-10-16

申请号：US12868577

申请日：2010-08-25

申请人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

发明人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

IPC分类号： G02B6/43

CPC分类号： H01L25/0657 ,  G02B6/43 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/6627 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/1903 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/014

摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a stepped terrace. A high-bandwidth ramp component, which is positioned approximately parallel to the stepped terrace, is mechanically coupled to the semiconductor dies. Furthermore, the ramp component includes an optical waveguide that conveys the optical signal, and an optical coupling component that optically couples the optical signal to one of the semiconductor dies, thereby facilitating high-bandwidth communication of the optical signal between the semiconductor die and the ramp component.

摘要翻译： 描述了斜坡堆叠芯片封装。 该芯片封装包括在水平方向上彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定阶梯式台阶。 位于大致平行于阶梯式台阶的高带宽斜坡部件机械耦合到半导体管芯。 此外，斜坡部件包括传送光信号的光波导和光耦合部件，其将光信号光耦合到半导体管芯之一，从而有助于半导体管芯和斜坡之间的光信号的高带宽通信 零件。

公开(公告)号：US20120049376A1

公开(公告)日：2012-03-01

申请号：US12873945

申请日：2010-09-01

申请人： John A. Harada ,  Robert J. Drost ,  David C. Douglas

发明人： John A. Harada ,  Robert J. Drost ,  David C. Douglas

IPC分类号： H01L23/498 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/42 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/06155 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16265 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92143 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19102

摘要： An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terraced at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a housing having another stepped terrace. This other stepped terrace may include a sequence of steps in the vertical direction, which are offset from each other in the horizontal direction. Furthermore, the housing may be configured to mate with the set of semiconductor dies such that the set of semiconductor dies are arranged in the stack in the vertical direction. For example, the other stepped terrace may approximately be a mirror image of the stepped terrace.

摘要翻译： 描述了使用组装部件组装芯片封装的组装部件和技术。 该芯片封装包括沿垂直方向布置成堆叠的一组半导体管芯，它们在水平方向上彼此偏移，以限定在垂直堆叠的一侧上阶梯状梯度。 此外，可以使用组件部件组装芯片封装。 特别地，组件部件可以包括具有另一阶梯式台阶的壳体。 该另外的阶梯式平台可以包括在水平方向上彼此偏移的垂直方向的一系列步骤。 此外，壳体可以被配置为与该组半导体管芯配合，使得该组半导体管芯沿着垂直方向布置在堆叠中。 例如，其他阶梯式露台大概可以是阶梯式露台的镜像。

公开(公告)号：US20120056327A1

公开(公告)日：2012-03-08

申请号：US12874446

申请日：2010-09-02

申请人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

发明人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  G02B6/43 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L29/0657 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16135 ,  H01L2224/16151 ,  H01L2224/1703 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81141 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/8185 ,  H01L2224/819 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83193 ,  H01L2224/8385 ,  H01L2225/06531 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/1015 ,  H01L2924/10155 ,  H01L2924/151

摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

摘要翻译： 描述了斜坡堆叠芯片封装。 该芯片封装包括在水平方向彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定具有暴露焊盘的露台。 位于大致平行于平台的高带宽斜坡部件被电气和机械耦合到暴露的焊盘。 例如，斜坡部件可以使用：焊料，微弹簧和/或各向异性导电膜耦合到半导体管芯。 此外，每个半导体管芯包括静态弯曲部，使得每个半导体管芯的端部段平行于该方向，并机械耦合到斜坡部件。 这些端段可以促进芯片和斜坡部件之间的信号的高带宽通信，例如通过接近通信。

公开(公告)号：US20120051695A1

公开(公告)日：2012-03-01

申请号：US12868577

申请日：2010-08-25

申请人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

发明人： John A. Harada ,  David C. Douglas ,  Robert J. Drost

IPC分类号： G02B6/26

CPC分类号： H01L25/0657 ,  G02B6/43 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/6627 ,  H01L2224/131 ,  H01L2224/14155 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2924/1903 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/014

摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a stepped terrace. A high-bandwidth ramp component, which is positioned approximately parallel to the stepped terrace, is mechanically coupled to the semiconductor dies. Furthermore, the ramp component includes an optical waveguide that conveys the optical signal, and an optical coupling component that optically couples the optical signal to one of the semiconductor dies, thereby facilitating high-bandwidth communication of the optical signal between the semiconductor die and the ramp component.

摘要翻译： 描述了斜坡堆叠芯片封装。 该芯片封装包括在水平方向上彼此偏移的半导体管芯或芯片的垂直堆叠，从而限定阶梯式台阶。 位于大致平行于阶梯式台阶的高带宽斜坡部件机械耦合到半导体管芯。 此外，斜坡部件包括传送光信号的光波导和光耦合部件，其将光信号光耦合到半导体管芯之一，从而有助于半导体管芯和斜坡之间的光信号的高带宽通信 零件。

公开(公告)号：US07949436B2

公开(公告)日：2011-05-24

申请号：US11437456

申请日：2006-05-19

申请人： Robert J. Drost ,  Ronald Ho ,  David C. Douglas

发明人： Robert J. Drost ,  Ronald Ho ,  David C. Douglas

IPC分类号： G05D1/02

CPC分类号： H05K3/303 ,  G02B6/4226 ,  H01L22/12 ,  H01L24/01 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06534 ,  H01L2225/06593 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0239 ,  H05K2201/10083 ,  H05K2201/10151 ,  H05K2201/10674 ,  H05K2203/166 ,  Y02P70/613 ,  Y10T29/49133

摘要： One embodiment of the present invention provides a system that automatically detects and corrects a misalignment of a semiconductor chip. During operation, the system uses a position-detection mechanism integrated with the chip to determine the misalignment of the chip from a desired alignment for the chip. Next, the system uses an actuation mechanism integrated with the chip to automatically correct the misalignment, thereby improving performance and reliability of the chip.

摘要翻译： 本发明的一个实施例提供一种自动检测和校正半导体芯片的未对准的系统。 在操作期间，系统使用与芯片集成的位置检测机构来确定芯片与芯片的期望对准的未对准。 接下来，系统使用与芯片集成的致动机构来自动校正未对准，从而提高芯片的性能和可靠性。

公开(公告)号：US20110018120A1

公开(公告)日：2011-01-27

申请号：US12507349

申请日：2009-07-22

申请人： Robert J. Drost ,  James G. Mitchell ,  David C. Douglas

发明人： Robert J. Drost ,  James G. Mitchell ,  David C. Douglas

IPC分类号： H01L23/538

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L23/642 ,  H01L23/645 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/72 ,  H01L24/90 ,  H01L25/0652 ,  H01L29/0657 ,  H01L2223/6638 ,  H01L2224/13099 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01067 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package is described. This chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, electrically couples to the exposed pads. For example, the ramp component may be electrically coupled to the semiconductor dies using: microsprings, an anisotropic film, and/or solder. Consequently, the electrical contacts may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. By removing the need for costly and area-consuming through-silicon vias (TSVs) in the semiconductor dies, the chip package facilitates chips to be stacked in a manner that provides high bandwidth and low cost.

摘要翻译： 描述了芯片封装。 该芯片封装包括彼此偏移的半导体管芯或芯片堆叠，由此限定具有暴露焊盘的露台。 位于大致平行于平台的高带宽斜坡部件电耦合到暴露的焊盘。 例如，斜坡部件可以使用：微弹簧，各向异性膜和/或焊料电耦合到半导体管芯。 因此，电触点可以具有导电性，电容性或通常的复阻抗。 此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。 通过消除对半导体管芯中昂贵且耗费大量的硅通孔（TSV）的需求，芯片封装便于以提供高带宽和低成本的方式堆叠芯片。

公开(公告)号：US07763396B2

公开(公告)日：2010-07-27

申请号：US11355757

申请日：2006-02-16

申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

IPC分类号： G03F9/00

CPC分类号： G03F7/70433

摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。

公开(公告)号：US20100244288A1

公开(公告)日：2010-09-30

申请号：US12813808

申请日：2010-06-11

申请人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

发明人： David C. Douglas ,  Ronald Ho ,  Robert J. Drost

IPC分类号： H01L23/544 ,  G03B27/52

CPC分类号： G03F7/70433

摘要： A system that fabricates a semiconductor chip. The system places patterns for components which require fine line-widths within a high resolution region of a reticle, wherein the high resolution region provides sharp focus for a given wavelength of light used by the lithography system. At the same time, the system places patterns for components which do not require fine line-widths outside of the high-resolution region of the reticle, thereby utilizing the region outside of the high-resolution region of the reticle instead of avoiding the region. Note that the coarseness for components placed outside of the high resolution region of the reticle is increased to compensate for the loss of optical focus outside of the high resolution region.

摘要翻译： 制造半导体芯片的系统。 系统将要求精细线宽的部件的图案放置在标线的高分辨率区域内，其中高分辨率区域为光刻系统使用的给定波长的光提供清晰的焦点。 同时，系统将不需要精细线宽的部件的图案放置在标线片的高分辨率区域之外，从而利用分划板的高分辨率区域之外的区域，而不是避开该区域。 注意，放大在分划板的高分辨率区域之外的分量的粗糙度被增加以补偿高分辨率区域外的光学焦点的损失。