SEMICONDUCTOR PACKAGE INCLUDING REDISTRIBUTION PATTERN AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING REDISTRIBUTION PATTERN AND METHOD OF MANUFACTURING THE SAME 审中-公开
    包括重新分配图案的半导体封装及其制造方法

    公开(公告)号:US20080048322A1

    公开(公告)日:2008-02-28

    申请号:US11837577

    申请日:2007-08-13

    Abstract: A semiconductor device package includes a substrate, first and second chip pads spaced apart over a surface of the substrate, and an insulating layer located over the surface of the substrate. The insulating layer includes a stepped upper surface defined by at least a lower reference potential line support surface portion, and an upper signal line support surface portion, where a thickness of the insulating layer at the lower reference potential line support surface portion is less than a thickness of the insulating layer at the upper signal line support surface portion. The package further includes a conductive reference potential line electrically connected to the first chip pad and located on the lower reference potential support surface portion of the insulating layer, a conductive signal line electrically connected to the second chip pad and located on the upper signal line support surface portion, and first and second external terminals electrically connected to the conductive reference potential line and the conductive signal line, respectively.

    Abstract translation: 半导体器件封装包括衬底,在衬底的表面上间隔开的第一和第二芯片焊盘以及位于衬底表面上的绝缘层。 绝缘层包括由至少一个下参考电位线支撑表面部分限定的阶梯状上表面和上信号线支撑表面部分,其中下参考电位线支撑表面部分处的绝缘层的厚度小于 上部信号线支撑表面部分处的绝缘层的厚度。 所述封装还包括电连接到所述第一芯片焊盘并且位于所述绝缘层的下参考电位支撑表面部分上的导电参考电位线,电连接到所述第二芯片焊盘并位于所述上信号线支撑件上的导电信号线 表面部分以及分别电连接到导电参考电位线和导电信号线的第一和第二外部端子。

    SEMICONDUCTOR CHIPS HAVING REDISTRIBUTED POWER/GROUND LINES DIRECTLY CONNECTED TO POWER/GROUND LINES OF INTERNAL CIRCUITS AND METHODS OF FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR CHIPS HAVING REDISTRIBUTED POWER/GROUND LINES DIRECTLY CONNECTED TO POWER/GROUND LINES OF INTERNAL CIRCUITS AND METHODS OF FABRICATING THE SAME 有权
    具有直接连接到内部电路的电源/接地线的重新分配的电源/接地线的半导体器件及其制造方法

    公开(公告)号:US20090212414A1

    公开(公告)日:2009-08-27

    申请号:US12431956

    申请日:2009-04-29

    Applicant: Jong-Joo LEE

    Inventor: Jong-Joo LEE

    Abstract: Provided are embodiments of semiconductor chips having a redistributed metal interconnection directly connected to power/ground lines of an internal circuit are provided. Embodiments of the semiconductor chips include an internal circuit formed on a semiconductor substrate. A chip pad is disposed on the semiconductor substrate. The chip pad is electrically connected to the internal circuit through an internal interconnection. A passivation layer is provided over the chip pad. A redistributed metal interconnection is provided on the passivation layer. The redistributed metal interconnection directly connects the internal interconnection to the chip pad through a via-hole and a chip pad opening, which penetrate at least the passivation layer. Methods of fabricating the semiconductor chip are also provided.

    Abstract translation: 提供了具有直接连接到内部电路的电源/接地线的重分布金属互连的半导体芯片的实施例。 半导体芯片的实施例包括形成在半导体衬底上的内部电路。 芯片焊盘设置在半导体衬底上。 芯片焊盘通过内部互连电连接到内部电路。 钝化层设置在芯片焊盘的上方。 在钝化层上设置重新分布的金属互连。 再分布的金属互连通过穿孔至少钝化层的通孔和芯片焊盘开口将内部互连直接连接到芯片焊盘。 还提供了制造半导体芯片的方法。

    STACK CHIP AND STACK CHIP PACKAGE HAVING THE SAME
    4.
    发明申请
    STACK CHIP AND STACK CHIP PACKAGE HAVING THE SAME 有权
    堆叠芯片和堆叠芯片包装

    公开(公告)号:US20090065950A1

    公开(公告)日:2009-03-12

    申请号:US12267343

    申请日:2008-11-07

    Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

    Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘,输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

    STACK CHIP AND STACK CHIP PACKAGE HAVING THE SAME
    7.
    发明申请
    STACK CHIP AND STACK CHIP PACKAGE HAVING THE SAME 有权
    堆叠芯片和堆叠芯片包装

    公开(公告)号:US20070170575A1

    公开(公告)日:2007-07-26

    申请号:US11627791

    申请日:2007-01-26

    Abstract: Provided are a stack chip and a stack chip package having the stack chip. Internal circuits of two semiconductor chips are electrically connected to each other through an input/output buffer connected to an external connection terminal. The semiconductor chip has chip pads, input/output buffers and internal circuits connected through circuit wirings. The semiconductor chip also has connection pads connected to the circuit wirings connecting the input/output buffers to the internal circuits. The semiconductor chips include a first chip and a second chip. The connection pads of the first chip are electrically connected to the connection pads of the second chip through electrical connection means. Input signals input through the external connection terminals are input to the internal circuits of the first chip or the second chip via the chip pads and the input/output buffers of the first chip, and the connection pads of the first chip and the second chip.

    Abstract translation: 提供了具有堆叠芯片的堆叠芯片和堆叠芯片封装。 两个半导体芯片的内部电路通过连接到外部连接端子的输入/输出缓冲器彼此电连接。 半导体芯片具有芯片焊盘,输入/输出缓冲器和通过电路布线连接的内部电路。 半导体芯片还具有连接到将输入/输出缓冲器连接到内部电路的电路布线的连接焊盘。 半导体芯片包括第一芯片和第二芯片。 第一芯片的连接焊盘通过电连接装置电连接到第二芯片的连接焊盘。 通过外部连接端子输入的输入信号经由芯片焊盘和第一芯片的输入/输出缓冲器以及第一芯片和第二芯片的连接焊盘输入到第一芯片或第二芯片的内部电路。

    CHIP STACK PACKAGE
    8.
    发明申请
    CHIP STACK PACKAGE 有权
    芯片堆栈包

    公开(公告)号:US20110316159A1

    公开(公告)日:2011-12-29

    申请号:US13224670

    申请日:2011-09-02

    Abstract: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

    Abstract translation: 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片,以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极,通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成,并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面,而不管其电阻率如何。

    CHIP STACK PACKAGE
    9.
    发明申请
    CHIP STACK PACKAGE 有权
    芯片堆栈包

    公开(公告)号:US20090108469A1

    公开(公告)日:2009-04-30

    申请号:US12171035

    申请日:2008-07-10

    Abstract: A chip stack package includes a plurality of chips that are stacked by using adhesive layers as intermediary media, and a through via electrode formed through the chips to electrically couple the chips. The through via electrode is classified as a power supply through via electrode, a ground through via electrode, or a signal transfer through via electrode. The power supply through via electrode and the ground through via electrode are formed of a first material such as copper, and the signal transfer through via electrode is formed of second material such as polycrystalline silicon doped with impurities. The signal transfer through via electrode may have a diametrically smaller cross section than that of each of the power supply through via electrode and the ground through via electrode regardless of their resistivities.

    Abstract translation: 芯片堆叠包括通过使用粘合剂层作为中间介质堆叠的多个芯片,以及通过芯片形成的通孔电极以电耦合芯片。 通孔电极通过通孔电极,通过通孔电极的接地或通过通孔电极的信号传输分类为电源。 通过通孔电极和通过通孔电极的接地的电源由诸如铜的第一材料形成,并且通过通孔电极的信号传输由掺杂杂质的多晶硅等第二材料形成。 通过通孔电极的信号传输可以具有比通过通孔电极和通过通孔电极的接地的每个电源的直径更小的横截面,而不管其电阻率如何。

    PRINTED CIRCUIT BOARD HAVING COPLANAR LC BALANCE
    10.
    发明申请
    PRINTED CIRCUIT BOARD HAVING COPLANAR LC BALANCE 有权
    印刷电路板有共同的LC平衡

    公开(公告)号:US20080142248A1

    公开(公告)日:2008-06-19

    申请号:US11945874

    申请日:2007-11-27

    Applicant: Jong-Joo LEE

    Inventor: Jong-Joo LEE

    Abstract: Provided is a printed circuit board having coplanar LC balance, comprising: an insulation layer, printed circuit patterns formed on the insulation layer, power source wirings supplying power in the printed circuit patterns, and at least three signal wirings formed between the power source wirings, wherein widths of signal wirings far from the power source wirings are wider than widths of signal wirings adjacent to the power source wirings to achieve LC balance, thereby reducing the skew between signal wirings and improving the quality of signal transfer.

    Abstract translation: 提供一种具有共面LC平衡的印刷电路板,包括:绝缘层,形成在绝缘层上的印刷电路图案,在印刷电路图案中供电的电源布线以及形成在电源布线之间的至少三个信号布线, 其中远离电源布线的信号布线的宽度宽于与电源布线相邻的信号布线的宽度,以实现LC平衡,从而减少信号布线之间的偏斜并提高信号传输的质量。

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