公开(公告)号：US20060280707A1

公开(公告)日：2006-12-14

申请号：US10544912

申请日：2003-04-23

申请人： Jong-ho Park ,  Chang-koo Shim ,  Sang-Uk Chung

发明人： Jong-ho Park ,  Chang-koo Shim ,  Sang-Uk Chung

IPC分类号： A61K8/00

CPC分类号： A61K8/418 ,  A61K8/20 ,  A61K8/31 ,  A61K8/35 ,  A61K8/44 ,  A61K8/49 ,  A61K8/64 ,  A61K2800/42 ,  A61K2800/45 ,  A61K2800/88 ,  A61Q5/04

摘要： The present invention relates to compositions of first agents of a permanent hair waving agent and a hair straightener for self-diagnosis with a reducing catalyst, respectively, and their manufacturing methods thereof. More specifically, the present invention relates to compositions of first agents a permanent hair waving agent and a hair straightener for self-diagnosis with a reducing catalyst, respectively, and their manufacturing methods thereof, wherein each of the first agents is a reducing agent prepared in two different solutions of A and B and mixed in a predetermined ratio immediately prior to use. Upon mixing, the first agent gives rise to a peculiar color thus enabling to identify both active ingredients and the properties of the solutions being used well in advance of hair styling performance -+y assisting proper selection of a permanent hair waving agent and a hair ,˜ner most suitable for each hair kind thus securing safe performance of hair a also preventing hair damage.

摘要翻译： 本发明涉及永久性头发挥发剂的第一种试剂和用还原催化剂自我诊断的直发器的组合物及其制造方法。 更具体地，本发明涉及分别用还原催化剂自诊断的永久性头发挥发剂和直发器的第一试剂的组合物及其制备方法，其中每种第一试剂是制备于 两种不同的A和B溶液，并在使用前立即以预定比例混合。 在混合时，第一种药剂产生特殊的颜色，从而能够在头发造型性能之前很好地鉴别活性成分和所使用溶液的性质 - + y帮助正确选择永久性头发发泡剂和头发， 〜最适合每一种头发，从而确保头发的安全性能也可以防止毛发损伤。

公开(公告)号：US08330218B2

公开(公告)日：2012-12-11

申请号：US12870913

申请日：2010-08-30

申请人： Jong-ho Park ,  Hyi-Jeong Park ,  Hye-mi Kim ,  Chang-Ki Jeon

发明人： Jong-ho Park ,  Hyi-Jeong Park ,  Hye-mi Kim ,  Chang-Ki Jeon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/8249 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7809 ,  H01L29/7812

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

公开(公告)号：US06229775B1

公开(公告)日：2001-05-08

申请号：US08225322

申请日：1994-04-08

申请人： Jong-ho Park

发明人： Jong-ho Park

IPC分类号： G11B70045

CPC分类号： G11B7/126 ,  G11B19/04

摘要： A driving method and apparatus for a light source element of an optical pickup for reading and writing data from and to an optical data includes generating an error signal when a tracking error signal is higher than a first level or is lower than a second level and, if the error signal is active, supplying the light source element with a driving signal suitable for data read operations independent of whether the user selects read mode or write mode. As a result, when there is a tracking error the power of the device signal corresponds to that normally presented during a read mode, and this power is insufficient to write data onto the disc. Thus, data is not written over other desired data when an abnormal tracking error occurs.

摘要翻译： 用于从光学数据读取和写入光学数据的光学拾取器的光源元件的驱动方法和装置包括当跟踪误差信号高于第一电平或低于第二电平时产生误差信号， 如果误差信号有效，则为光源元件提供适合于数据读取操作的驱动信号，而与用户是否选择读取模式或写入模式无关。 结果，当存在跟踪误差时，设备信号的功率对应于在读取模式期间通常呈现的功率，并且该功率不足以将数据写入到盘上。 因此，当出现异常跟踪错误时，数据不会写入其他所需数据。

公开(公告)号：US5444005A

公开(公告)日：1995-08-22

申请号：US246277

申请日：1994-05-19

申请人： Yun-gi Kim ,  Fui-song Kim ,  Jin-seok Choi ,  Jong-ho Park

发明人： Yun-gi Kim ,  Fui-song Kim ,  Jin-seok Choi ,  Jong-ho Park

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L28/92 ,  Y10S438/947

摘要： A method for manufacturing a capacitor of a semiconductor memory device. A conductive layer is formed on the semiconductor substrate and a photoresist pattern is formed on the conductive layer. The conductive layer is etched, using the photoresist pattern as a mask to form a first step-portion in the conductive layer. A first spacer is formed on a sidewall of the photoresist pattern, which may be formed by flowing the photoresist pattern. The conductive layer is etched, using the first spacer as a mask, to form a second step-portion in the conductive layer. The photoresist pattern and the first spacer is removed. A first material layer is formed on the entire surface of the resultant structure and etched to form a second spacer on the sidewalls of the first and second step-portions. The conductive layer is etched, using the second spacer as a mask, to form a storage electrode of a capacitor. Cell capacitance may be increased by a simple process, and the heat cycle may be reduced.

摘要翻译： 一种半导体存储器件的电容器的制造方法。 在半导体衬底上形成导电层，并且在导电层上形成光刻胶图案。 使用光致抗蚀剂图案作为掩模蚀刻导电层，以在导电层中形成第一台阶部分。 在光致抗蚀剂图案的侧壁上形成第一间隔物，其可以通过使光致抗蚀剂图案流动而形成。 使用第一间隔件作为掩模蚀刻导电层，以在导电层中形成第二台阶部分。 去除光致抗蚀剂图案和第一间隔物。 第一材料层形成在所得结构的整个表面上并被蚀刻以在第一和第二台阶部分的侧壁上形成第二间隔物。 使用第二间隔物作为掩模蚀刻导电层，以形成电容器的存储电极。 可以通过简单的工艺来增加电池电容，并且可以减少热循环。

公开(公告)号：US20110240832A1

公开(公告)日：2011-10-06

申请号：US13124319

申请日：2009-10-15

申请人： Shoji Kawahito ,  Jong-ho Park ,  Satoshi Aoyama ,  Keigo Isobe

发明人： Shoji Kawahito ,  Jong-ho Park ,  Satoshi Aoyama ,  Keigo Isobe

IPC分类号： H01L27/146 ,  H03M1/12

CPC分类号： H03M1/0695 ,  H03M1/123 ,  H03M1/403 ,  H04N5/3658 ,  H04N5/3745 ,  H04N5/378

摘要： A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).

摘要翻译： 提供了可以减少用于D / A转换的参考电压数量的循环A / D转换器。 循环A / D转换器（11）包括增益级（15），A / D转换器电路（17），逻辑电路（19）和D / A转换器电路（21）。 在增益级（15）的操作动作中，通过使用运算放大器电路（23）和电容器（25,27,29）产生运算值（VOP）。 增益级（15）通过切换要施加到电容器（25,27）的两种电压信号（VDA1，VDA2）来接收来自D / A转换器电路（21）的三种电压信号， 开关电路（31）。 也就是说，D / A转换器电路（21）响应于数字信号（B0，B1）的值（D = 2）向电容器（25,27）提供电压信号（VRH），提供电压 分别响应信号（B0，B1）的值（D = 1）向电容器（25,27）输出信号（VRH，VRL），并将电压信号（VRL）提供给电容器（25,27） 响应于信号（B0，B1）的值（D = 0）27）。

公开(公告)号：US07803676B2

公开(公告)日：2010-09-28

申请号：US12414172

申请日：2009-03-30

申请人： Jong-ho Park ,  Chang-Ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

发明人： Jong-ho Park ,  Chang-Ki Jeon ,  Hyi-Jeong Park ,  Hye-mi Kim

IPC分类号： H01L21/8238 ,  H01L21/331 ,  H01L21/8222

CPC分类号： H01L21/8249 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7809 ,  H01L29/7812

摘要： Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device using a DMOS device includes: a semiconductor substrate, in which a first conductive type well is formed; a first conductive type gate electrode formed on the semiconductor substrate with a gate insulating layer intervening between the gate electrode and the semiconductor substrate; a second conductive type body electrode formed on the semiconductor substrate and separated from the gate electrode; a first conductive type drain electrode formed on the semiconductor substrate and separated from the gate electrode and the body electrode; a second conductive type first body region formed in the well under the body electrode; a second conductive type second body region extending from the first body region to the gate insulating layer and formed in the well; a first conductive type source region formed in the second body region and extending from the first body region to the gate insulating layer; and a first conductive type source electrode extending from the source region to surround the gate electrode on the semiconductor substrate with an insulating layer intervening between the source electrode and gate electrode.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 使用DMOS器件的半导体器件包括：形成第一导电型阱的半导体衬底; 形成在所述半导体衬底上的第一导电型栅极电极，所述栅极绝缘层介于所述栅电极和所述半导体衬底之间; 形成在所述半导体基板上并与所述栅电极分离的第二导电型体电极; 形成在所述半导体基板上并与所述栅电极和所述主体电极分离的第一导电型漏电极; 形成在所述体电极下方的所述阱内的第二导电型第一体区域; 第二导电类型的第二主体区域，其从所述第一主体区域延伸到所述栅极绝缘层并形成在所述阱中; 形成在所述第二主体区域中并从所述第一主体区域延伸到所述栅极绝缘层的第一导电型源极区域; 以及第一导电型源电极，其从所述源极区域延伸，以在所述半导体衬底上围绕所述栅极电极，所述绝缘层介于所述源电极和栅电极之间。

公开(公告)号：US5355020A

公开(公告)日：1994-10-11

申请号：US910894

申请日：1992-07-08

申请人： Sang-in Lee ,  Jeong-in Hong ,  Jong-ho Park

发明人： Sang-in Lee ,  Jeong-in Hong ,  Jong-ho Park

IPC分类号： H01L23/52 ,  H01L21/027 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/0276 ,  H01L21/28512 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53271 ,  H01L2924/0002

摘要： A wiring layer of a semiconductor device having a novel contact structure is disclosed. The semiconductor device includes a semiconductor substrate, an insulating layer having an opening (contact hole or via) and a first conductive layer formed on the insulating layer which completely fills the opening. The first conductive layer does not produce any Si precipitates in a subsequent heat-treating step for filling the opening with the first conductive layer material. The semiconductor device may further include a second conductive layer having a planarized surface on the first conductive layer. This improves subsequent photolithography. An anti-reflective layer may be formed on the second conductive layer for preventing an unwanted reflection during a photo lithography process. The semiconductor device preferably includes a diffusion barrier layer under the first conductive layer and on the semiconductor substrate, on the insulating layer, and on the inner surface of the opening which prevents a reaction between the first conductive layer and the semiconductor substrate or the insulating layer. A method for forming the wiring layer is also disclosed. Providing a semiconductor device with the wiring layer reduces the leakage current by preventing an Al spiking. Since the first conductive layer undergoes a heat-treatment step at a temperature below the melting point, while flowing into the opening and completely filling it with the first conductive layer material, no void is formed in the opening. Good semiconductor device reliability is ensured in spite of the contact hole being less than 1 .mu.m in size and having an aspect ratio greater than 1.0.

摘要翻译： 公开了具有新型接触结构的半导体器件的布线层。 半导体器件包括半导体衬底，具有开口（接触孔或通孔）的绝缘层和形成在绝缘层上的完全填充开口的第一导电层。 在随后的用第一导电层材料填充开口的热处理步骤中，第一导电层不产生任何Si沉淀物。 半导体器件还可以包括在第一导电层上具有平坦化表面的第二导电层。 这改善了随后的光刻。 可以在第二导电层上形成抗反射层，以防止在光刻工艺期间不期望的反射。 半导体器件优选地包括在第一导电层下方，半导体衬底上的绝缘层上的扩散阻挡层，以及防止第一导电层与半导体衬底或绝缘层之间的反应的开口内表面 。 还公开了一种用于形成布线层的方法。 提供具有布线层的半导体器件通过防止Al尖峰来减少泄漏电流。 由于第一导电层在低于熔点的温度下经历热处理步骤，同时流入开口并用第一导电层材料完全填充，因此在开口中不形成空隙。 尽管接触孔的尺寸小于1μm，纵横比大于1.0，仍然保证良好的半导体器件的可靠性。

公开(公告)号：US08581171B2

公开(公告)日：2013-11-12

申请号：US13124319

申请日：2009-10-15

申请人： Shoji Kawahito ,  Jong-ho Park ,  Satoshi Aoyama ,  Keigo Isobe

发明人： Shoji Kawahito ,  Jong-ho Park ,  Satoshi Aoyama ,  Keigo Isobe

IPC分类号： H01L27/146

CPC分类号： H03M1/0695 ,  H03M1/123 ,  H03M1/403 ,  H04N5/3658 ,  H04N5/3745 ,  H04N5/378

摘要： A cyclic A/D converter which can reduce the number of reference voltages for D/A conversion is provided. The cyclic A/D converter (11) comprises a gain stage (15), an A/D converter circuit (17), a logic circuit (19), and a D/A converter circuit (21). In an operational action of the gain stage (15), an operational value (VOP) is generated by the use of an operational amplifier circuit (23) and capacitors (25, 27, 29). The gain stage (15) operates as receiving three kinds of voltage signal from the D/A converter circuit (21) by the switching of two kinds of voltage signal (VDA1, VDA2) to be applied to the capacitors (25, 27) in a switching circuit (31). That is, the D/A converter circuit (21) provides a voltage signal (VRH) to the capacitors (25, 27), in response to a value (D=2) of a digital signal (B0, B1), provides voltage signals (VRH, VRL) to the capacitors (25, 27), respectively, in response to a value (D=1) of the signal (B0, B1), and provides the voltage signal (VRL) to the capacitors (25, 27), in response to a value (D=0) of the signal (B0, B1).

摘要翻译： 提供了可以减少用于D / A转换的参考电压数量的循环A / D转换器。 循环A / D转换器（11）包括增益级（15），A / D转换器电路（17），逻辑电路（19）和D / A转换器电路（21）。 在增益级（15）的操作动作中，通过使用运算放大器电路（23）和电容器（25,27,29）产生运算值（VOP）。 增益级（15）通过切换要施加到电容器（25,27）的两种电压信号（VDA1，VDA2）来接收来自D / A转换器电路（21）的三种电压信号， 开关电路（31）。 也就是说，D / A转换器电路（21）响应于数字信号（B0，B1）的值（D = 2）向电容器（25,27）提供电压信号（VRH），提供电压 分别响应信号（B0，B1）的值（D = 1）向电容器（25,27）输出信号（VRH，VRL），并将电压信号（VRL）提供给电容器（25,27） 响应于信号（B0，B1）的值（D = 0）27）。

公开(公告)号：US08242007B2

公开(公告)日：2012-08-14

申请号：US12401693

申请日：2009-03-11

申请人： Jong-ho Park ,  Chang-ki Jeon ,  Hyi-jeong Park

发明人： Jong-ho Park ,  Chang-ki Jeon ,  Hyi-jeong Park

IPC分类号： H01L27/06 ,  H01L21/60

CPC分类号： H01L21/8249 ,  H01L21/2256 ,  H01L21/823814 ,  H01L27/0623

摘要： Provided are a semiconductor device including a source/drain and a gate formed using a doped polysilicon process, and a method of fabricating the semiconductor device. The method comprises: forming a gate insulating layer on a part of an active region on a first conductivity type epitaxial layer; forming a conductive layer on the epitaxial layer; implanting high concentration impurities of a second conductivity type a first portion of the conductive layer on the gate insulating layer and second portions of the conductive layer on both sides of the first insulating layer; patterning the conductive layer; forming a second insulating layer on the epitaxial layer and high concentration impurity regions of the second conductivity type below the second conductive pattern; and implanting low-concentration impurities of the second conductivity type into the epitaxial layer between a gate structure and the high concentration impurity regions.

摘要翻译： 提供了包括使用掺杂多晶硅工艺形成的源极/漏极和栅极的半导体器件，以及制造半导体器件的方法。 该方法包括：在第一导电型外延层的有源区的一部分上形成栅极绝缘层; 在外延层上形成导电层; 将第二导电类型的高浓度杂质注入到第一绝缘层的栅绝缘层上的导电层的第一部分和导电层的第二部分上; 图案化导电层; 在所述外延层上形成第二绝缘层，在所述第二导电图案之下形成所述第二导电类型的高浓度杂质区; 以及将第二导电类型的低浓度杂质注入到栅极结构和高浓度杂质区之间的外延层中。

公开(公告)号：US5357405A

公开(公告)日：1994-10-18

申请号：US142922

申请日：1993-10-29

申请人： Jong-ho Park

发明人： Jong-ho Park

IPC分类号： F21V7/00 ,  F21V8/00 ,  G02B6/00

CPC分类号： G02B6/0046 ,  G02B6/0055 ,  G02B6/002 ,  G02B6/0051 ,  G02B6/0061

摘要： A backlighting device for producing a uniform luminance throughout a screen for use in LCD devices includes a semicylindrical concave surface on a light-transmitting top face of a light-guiding plate, lamps installed near two opposed edges of the light-guiding plate, a light-diffusing plate on the top side of the light-guiding plate, a light-reflecting plate attached to the bottom face of the light-guiding plate, and reflecting film patterns between the light-guiding plate and the reflecting plate. The present invention provides for a simpler manufacture of the backlighting devices producing a high and uniform luminance.

摘要翻译： 用于在LCD器件中用于在整个屏幕上产生均匀亮度的背光装置包括在导光板的透光顶面上的半圆柱形凹面，安装在导光板两个相对边缘附近的灯， 在导光板的上侧的扩散板，安装在导光板的底面的光反射板，以及导光板和反射板之间的反射膜图案。 本发明提供了制造高均匀亮度的背光装置的更简单的制造方法。