公开(公告)号：US20140252656A1

公开(公告)日：2014-09-11

申请号：US14201756

申请日：2014-03-07

Applicant: Jong-joo LEE

Inventor： Jong-joo LEE

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package, comprising: a substrate; a first semiconductor chip; and at least one second semiconductor chip. The first semiconductor chip and the at least one second semiconductor chip are stacked on the substrate; the first semiconductor chip is electrically connected with the substrate; and an electrical connection of each second semiconductor chip is formed through a secondary input/output buffer of the first semiconductor chip.

Abstract translation: 一种半导体封装，包括：衬底; 第一半导体芯片; 和至少一个第二半导体芯片。 第一半导体芯片和至少一个第二半导体芯片堆叠在基板上; 第一半导体芯片与衬底电连接; 并且通过第一半导体芯片的次级输入/输出缓冲器形成每个第二半导体芯片的电连接。

公开(公告)号：US20090283894A1

公开(公告)日：2009-11-19

申请号：US12464921

申请日：2009-05-13

Applicant: Jong-joo LEE ,  Seung-duk Baek

Inventor： Jong-joo LEE ,  Seung-duk Baek

IPC: H01L23/52 ,  H05K1/14

CPC classification number: H05K1/115 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2223/6616 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/3011 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/0263 ,  H05K3/429 ,  H05K2201/09636

Abstract: A semiconductor chip package includes a signal interconnection penetrating a semiconductor chip and transmitting a signal to the semiconductor chip and a power interconnection and a ground interconnection penetrating the semiconductor and supplying power and ground to the semiconductor chip. The power interconnection and the ground interconnection are arranged to neighbor each other adjacent to the signal interconnection.

Abstract translation: 半导体芯片封装包括穿透半导体芯片并将信号传输到半导体芯片的信号互连以及穿透半导体的电源互连和接地互连，并向半导体芯片供电和接地。 电源互连和接地互连被布置成邻近信号互连相邻。

公开(公告)号：US20110309475A1

公开(公告)日：2011-12-22

申请号：US13080042

申请日：2011-04-05

Applicant: Jong-joo LEE

Inventor： Jong-joo LEE

IPC: H01L29/94

CPC classification number: H01L27/0688 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1069 ,  G11C7/1084 ,  G11C7/1096 ,  G11C8/06 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A three-dimensional (3D) semiconductor device including a plurality of stacked layers and a through-silicon via (TSV) electrically connecting the plurality of layers, in which in signal transmission among the plurality of layers, the TSV transmits a signal that swings in a range from an offset voltage that is higher than a ground voltage to a power voltage, thereby minimizing an influence of a metal-oxide-semiconductor (MOS) capacitance of TSV.

Abstract translation: 包括多个堆叠层的三维（3D）半导体器件和电连接多个层的贯穿硅通孔（TSV），其中在多个层之间的信号传输中，TSV发送摆动的信号 从高于接地电压的偏移电压到电源电压的范围，从而最小化TSV的金属氧化物半导体（MOS）电容的影响。

公开(公告)号：US20110183447A1

公开(公告)日：2011-07-28

申请号：US13014108

申请日：2011-01-26

Applicant: Jong-joo LEE

Inventor： Jong-joo LEE

IPC: H01L21/66 ,  H01L21/50

CPC classification number: H01L21/6835 ,  H01L21/76898 ,  H01L22/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A method of manufacturing a stacked semiconductor package in which a plurality of semiconductor chips are stacked includes preparing a first semiconductor chip including a first semiconductor device, a first penetration electrode, and a first connection unit electrically connected to the first semiconductor device or the first penetration electrode, attaching the first semiconductor chip to a base substrate with the first connection unit interposed therebetween, forming a first rewiring pattern and a first protection layer on the first semiconductor chip by using a printing method, wherein the first rewiring pattern is electrically connected to the first penetration electrode and the first protection layer partially covers the first rewiring pattern and exposes other portions of the first rewiring pattern, and attaching a second semiconductor chip including a second semiconductor device to the first semiconductor chip to electrically connect the second semiconductor device to the first rewiring pattern.

Abstract translation: 制造堆叠半导体封装的方法，其中堆叠多个半导体芯片包括制备包括第一半导体器件，第一穿透电极和第一连接单元的第一半导体芯片，该第一半导体芯片电连接到第一半导体器件或第一穿透 电极，将第一半导体芯片与第一连接单元插入到基底基板之间，通过使用打印方法在第一半导体芯片上形成第一重新布线图案和第一保护层，其中第一重新布线图案电连接到 第一穿透电极和第一保护层部分地覆盖第一重新布线图案并暴露第一重新布线图案的其他部分，并且将包括第二半导体器件的第二半导体芯片附接到第一半导体芯片以将第二半导体器件电连接到第一 重新布线图案