公开(公告)号：US20090124075A1

公开(公告)日：2009-05-14

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/768

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US07727877B2

公开(公告)日：2010-06-01

申请号：US12149014

申请日：2008-04-24

申请人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

发明人： Joon-Seok Kang ,  Sung Yi ,  Jong-Hwan Baek ,  Young-Do Kweon

IPC分类号： H01L21/445

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05611 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved.

摘要翻译： 公开了一种制造晶片级封装的方法，其可以包括：在半导体芯片的一侧上涂覆绝缘层，其一面形成电极焊盘，使得电极焊盘打开; 通过在所述半导体芯片的一侧上沉积导电金属形成晶种层; 形成与电极焊盘电连接的重新布线图案，通过选择性地电镀种子层作为电极; 形成与所述重新布线图案电连接的导电柱，通过所述种子层作为电极的选择性电镀; 并将种子层的部分去除到外部。 通过使用一个种子层形成再布线图案和金属柱，可以简化制造工艺，从而可以减少制造过程中的缺陷，并且可以提高产品的可靠性。

公开(公告)号：US07632709B2

公开(公告)日：2009-12-15

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

公开(公告)号：US20090087951A1

公开(公告)日：2009-04-02

申请号：US12149106

申请日：2008-04-25

申请人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

发明人： Hyung-Jin Jeon ,  Sung Yi ,  Young-Do Kweon ,  Jong-Yun Lee ,  Joon-Seok Kang ,  Seung-Wook Park

IPC分类号： H01L21/02

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L24/11 ,  H01L24/12 ,  H01L24/24 ,  H01L24/27 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517

摘要： A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.

摘要翻译： 公开了一种制造晶片级封装的方法。 该方法可以包括在晶片衬底上堆叠绝缘层; 处理绝缘层中的通孔; 在所述绝缘层上形成种子层; 在种子层上形成与再分布图案对应关系的电镀抗蚀剂; 通过电镀形成包括用于外部接触的端子的再分布图案; 并将导电球耦合到端子。 由于可以使用廉价的PCB工艺形成多个再分布层，所以可以降低制造成本，并且可以提高工艺的稳定性和效率。

公开(公告)号：US20080211083A1

公开(公告)日：2008-09-04

申请号：US12007590

申请日：2008-01-11

申请人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Suk-Youn Hong ,  Sun-Kyong Kim ,  Jong-Hwan Baek

发明人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Suk-Youn Hong ,  Sun-Kyong Kim ,  Jong-Hwan Baek

IPC分类号： H01L23/485 ,  H01L21/60

CPC分类号： H01L24/19 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/28 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83101 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being formed in the other surface of the second chip; encapsulating the second chip by coating the other surface of the PCB with an insulation material; and processing a first via by punching a hole on the insulation material, the first via being electrically interconnected to the pad, can perform stable handling in a process of mounting a semiconductor chip, make it unnecessary to add a process for chip encapsulation and realize a system in package having high density and high reliability.

摘要翻译： 公开了电子封装及其制造方法。 电子封装制造方法，其包括提供具有一个表面的印刷电路板（PCB），其上安装有第一芯片; 将第二芯片的一个表面附接在所述PCB的另一个表面上，衬垫形成在所述第二芯片的另一个表面中; 通过用绝缘材料涂覆PCB的另一表面来封装第二芯片; 并且通过冲压绝缘材料上的孔来处理第一通孔，第一通孔电连接到焊盘，可以在安装半导体芯片的过程中执行稳定的处理，使得不需要添加用于芯片封装的工艺，并实现 封装体系密度高，可靠性高。

公开(公告)号：US08779580B2

公开(公告)日：2014-07-15

申请号：US12010321

申请日：2008-01-23

申请人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

发明人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

IPC分类号： H01L23/10 ,  H01L23/34

CPC分类号： H05K1/0203 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/066 ,  Y10T29/49146

摘要： An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

摘要翻译： 公开了一种电子部件封装及其制造方法。 电子部件封装制造方法，其包括将电子部件安装在第一绝缘层的一个表面中; 将散热器与对应于电子部件的第一绝缘层的一个表面接合以覆盖电子部件，散热器形成有空腔; 用粘合剂填充空腔; 并且在第一绝缘层的另一个表面上形成电路图案，可以防止在粘合剂中产生空隙，使得处理稳定并且通过使形成有空腔的散热器覆盖电子元件的尺寸变小， 图案积聚并通过腔的一侧供应粘合剂，同时通过另一侧提供负压。

公开(公告)号：US20080212288A1

公开(公告)日：2008-09-04

申请号：US12010321

申请日：2008-01-23

申请人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

发明人： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

IPC分类号： H05K7/20 ,  H05K3/10

CPC分类号： H05K1/0203 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/066 ,  Y10T29/49146

摘要： An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

摘要翻译： 公开了一种电子部件封装及其制造方法。 电子部件封装制造方法，其包括将电子部件安装在第一绝缘层的一个表面中; 将散热器与对应于电子部件的第一绝缘层的一个表面接合以覆盖电子部件，散热器形成有空腔; 用粘合剂填充空腔; 并且在第一绝缘层的另一个表面上形成电路图案，可以防止在粘合剂中产生空隙，使得处理稳定并且通过使形成有空腔的散热器覆盖电子元件的尺寸变小， 图案积聚并通过腔的一侧供应粘合剂，同时通过另一侧提供负压。

公开(公告)号：US09209101B2

公开(公告)日：2015-12-08

申请号：US12892032

申请日：2010-09-28

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

IPC分类号： H01L23/552 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

CPC分类号： H01L23/3121 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.

摘要翻译： 公开了一种半导体封装和半导体封装的制造方法。 根据本发明的实施例的半导体封装包括形成有接地电路并且在一个表面上安装有半导体芯片的基板，形成在基板的另一表面上并连接的导电接地层 接地电路，密封接地层和其上安装有半导体芯片的基板的模制件和覆盖模制件并与接地层连接的导电屏蔽件。 利用根据本发明的实施例的半导体封装，即使在完全模制的结构中也可以进行屏蔽的接地，以及用于提高屏蔽性的双重屏蔽结构。

公开(公告)号：US20110298102A1

公开(公告)日：2011-12-08

申请号：US12892032

申请日：2010-09-28

申请人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

发明人： Do-Jae Yoo ,  Young-Do Kweon ,  Joon-Seok Kang ,  Chang-Bae Lee

IPC分类号： H01L23/552 ,  H01L21/02

CPC分类号： H01L23/3121 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/552 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.

摘要翻译： 公开了一种半导体封装和半导体封装的制造方法。 根据本发明的实施例的半导体封装包括形成有接地电路并且在一个表面上安装有半导体芯片的基板，形成在基板的另一表面上并连接的导电接地层 接地电路，密封接地层和其上安装有半导体芯片的基板的模制件和覆盖模制件并与接地层连接的导电屏蔽件。 利用根据本发明的实施例的半导体封装，即使在完全模制的结构中也可以进行屏蔽的接地，以及用于提高屏蔽性的双重屏蔽结构。

公开(公告)号：USD626588S1

公开(公告)日：2010-11-02

申请号：US29313583

申请日：2009-01-23

申请人： Jong-Kyu Kim ,  Joon-Seok Kang ,  Yun-Gi Hong

设计人： Jong-Kyu Kim ,  Joon-Seok Kang ,  Yun-Gi Hong