公开(公告)号：US08410465B2

公开(公告)日：2013-04-02

申请号：US12716948

申请日：2010-03-03

Applicant: Seung Seoup Lee ,  Jae Cheon Doh ,  In Kyung Park

Inventor： Seung Seoup Lee ,  Jae Cheon Doh ,  In Kyung Park

IPC: G01N21/86

CPC classification number: G01R31/309

Abstract: An apparatus for inspecting defects in a circuit pattern is described. The apparatus includes at least one laser unit for radiating a laser beam onto a first end of a circuit pattern formed on a substrate. The apparatus also includes a capacitor sensor disposed opposite a second end of the circuit pattern, which is connected to the first end of the circuit pattern through a via hole, in a non-contact manner. The apparatus also includes a voltage source connected to the capacitor sensor and configured to apply a voltage. The apparatus also includes a measurement unit connected to the capacitor sensor and configured to detect variation in impedance generated in the capacitor sensor.

Abstract translation: 描述了用于检查电路图案中的缺陷的装置。 该装置包括用于将激光束照射到形成在基板上的电路图案的第一端上的至少一个激光单元。 该装置还包括电容传感器，该电容器传感器与电路图案的第二端相对设置，其以非接触方式通过通孔连接到电路图案的第一端。 该装置还包括连接到电容器传感器并被配置为施加电压的电压源。 该装置还包括连接到电容器传感器并被配置为检测在电容器传感器中产生的阻抗变化的测量单元。

公开(公告)号：US20100102445A1

公开(公告)日：2010-04-29

申请号：US12650610

申请日：2009-12-31

Applicant: Min-Kyo Cho ,  Jae-Cheon Doh ,  Young-Shin Kwon

Inventor： Min-Kyo Cho ,  Jae-Cheon Doh ,  Young-Shin Kwon

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H04N5/2251 ,  H01L27/14618 ,  H01L27/14806 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/49171 ,  H04N5/2253 ,  H04N5/2254 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.

Abstract translation: 在一个实施例中，小型化固态成像装置包括具有用于将半导体芯片安装在其中的空腔的主体。 主体具有向空腔延伸的伸出部分。 此外，引线设置在身体内。 引线的一端通过主体的顶表面暴露，而另一端通过主体的底表面暴露以与其电连接。

公开(公告)号：US20080211083A1

公开(公告)日：2008-09-04

申请号：US12007590

申请日：2008-01-11

Applicant: Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Suk-Youn Hong ,  Sun-Kyong Kim ,  Jong-Hwan Baek

Inventor： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Suk-Youn Hong ,  Sun-Kyong Kim ,  Jong-Hwan Baek

IPC: H01L23/485 ,  H01L21/60

CPC classification number: H01L24/19 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/28 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/83101 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic package and a manufacturing method thereof are disclosed. The electronic package manufacturing method, which includes providing a printed circuit board (PCB) having one surface on which a first chip is mounted; attaching one surface of a second chip on the other surface of the PCB, a pad being formed in the other surface of the second chip; encapsulating the second chip by coating the other surface of the PCB with an insulation material; and processing a first via by punching a hole on the insulation material, the first via being electrically interconnected to the pad, can perform stable handling in a process of mounting a semiconductor chip, make it unnecessary to add a process for chip encapsulation and realize a system in package having high density and high reliability.

Abstract translation: 公开了电子封装及其制造方法。 电子封装制造方法，其包括提供具有一个表面的印刷电路板（PCB），其上安装有第一芯片; 将第二芯片的一个表面附接在所述PCB的另一个表面上，衬垫形成在所述第二芯片的另一个表面中; 通过用绝缘材料涂覆PCB的另一表面来封装第二芯片; 并且通过冲压绝缘材料上的孔来处理第一通孔，第一通孔电连接到焊盘，可以在安装半导体芯片的过程中执行稳定的处理，使得不需要添加用于芯片封装的工艺，并实现 封装体系密度高，可靠性高。

公开(公告)号：US20050174469A1

公开(公告)日：2005-08-11

申请号：US11053209

申请日：2005-02-07

Applicant: Min-Kyo Cho ,  Jae-Cheon Doh ,  Young-Shin Kwon

Inventor： Min-Kyo Cho ,  Jae-Cheon Doh ,  Young-Shin Kwon

IPC: H01L27/14 ,  H01L23/00 ,  H01L23/02 ,  H01L23/04 ,  H01L23/12 ,  H01L23/50 ,  H01L27/146 ,  H01L27/148 ,  H01L31/0203 ,  H01L31/0232 ,  H04N5/225 ,  H04N5/335

CPC classification number: H04N5/2251 ,  H01L27/14618 ,  H01L27/14806 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/49171 ,  H04N5/2253 ,  H04N5/2254 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: In one embodiment, a miniaturized solid-state imaging apparatus includes a body having a cavity for mounting a semiconductor chip therein. The body has an overhanging portion extending toward the cavity. Further, a lead is disposed within the body. The lead has one end exposed through a top surface of the body and the other end exposed through a bottom surface of the body for electrical connection thereof.

Abstract translation: 在一个实施例中，小型化固态成像装置包括具有用于将半导体芯片安装在其中的空腔的主体。 主体具有向空腔延伸的伸出部分。 此外，引线设置在身体内。 引线的一端通过主体的顶表面暴露，而另一端通过主体的底表面暴露以与其电连接。

公开(公告)号：US08779580B2

公开(公告)日：2014-07-15

申请号：US12010321

申请日：2008-01-23

Applicant: Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

Inventor： Joon-Seok Kang ,  Sung Yi ,  Jae-Cheon Doh ,  Do-Jae Yoo ,  Sun-Kyong Kim ,  Jong-Hwan Baek

IPC: H01L23/10 ,  H01L23/34

CPC classification number: H05K1/0203 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K2201/066 ,  Y10T29/49146

Abstract: An electronic component package and a manufacturing method thereof are disclosed. The electronic component package manufacturing method, which includes mounting an electronic component in one surface of a first insulation layer; bonding a heat sink to the one surface of the first insulation layer, corresponding to the electronic component, to cover the electronic component, the heat sink being formed with a cavity; charging the cavity with an adhesive; and forming a circuit pattern in the other surface of the first insulation layer, can prevent a void from being generated in the adhesive, make the handling stable and make the size small by allowing the heat sink formed with the cavity to cover the electronic component before the pattern build-up and supplying the adhesive through one side of the cavity while providing negative pressure through the other side.

Abstract translation: 公开了一种电子部件封装及其制造方法。 电子部件封装制造方法，其包括将电子部件安装在第一绝缘层的一个表面中; 将散热器与对应于电子部件的第一绝缘层的一个表面接合以覆盖电子部件，散热器形成有空腔; 用粘合剂填充空腔; 并且在第一绝缘层的另一个表面上形成电路图案，可以防止在粘合剂中产生空隙，使得处理稳定并且通过使形成有空腔的散热器覆盖电子元件的尺寸变小， 图案积聚并通过腔的一侧供应粘合剂，同时通过另一侧提供负压。

公开(公告)号：US20110298103A1

公开(公告)日：2011-12-08

申请号：US12892411

申请日：2010-09-28

Applicant: Do-Jae YOO ,  Jae-Cheon Doh

Inventor： Do-Jae YOO ,  Jae-Cheon Doh

IPC: H01L23/552 ,  H01L21/02

CPC classification number: H01L23/3121 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/73253 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19107

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which has a ground circuit formed thereon, a semiconductor chip, which is mounted on the substrate, a conductive first shield, which is formed on an upper surface of the semiconductor chip and connected with the ground circuit, and a conductive second shield, which covers the substrate and the semiconductor chip and is connected with the first shield. With a semiconductor package in accordance with an embodiment of the present invention, grounding is possible between semiconductor chips because a shield is also formed on an upper surface of the semiconductor chip, and the shielding property can be improved by a double shielding structure.

Abstract translation: 公开了一种半导体封装和半导体封装的制造方法。 根据本发明的实施例的半导体封装包括其上形成有接地电路的基板，安装在基板上的半导体芯片，形成在半导体的上表面上的导电第一屏蔽 并且与接地电路连接，以及覆盖基板和半导体芯片并与第一屏蔽件连接的导电第二屏蔽件。 利用根据本发明的实施例的半导体封装，由于在半导体芯片的上表面上也形成屏蔽，所以可以在半导体芯片之间进行接地，并且可以通过双重屏蔽结构来提高屏蔽性能。

公开(公告)号：US20080063789A1

公开(公告)日：2008-03-13

申请号：US11980430

申请日：2007-10-31

Applicant: Ye-Chung Chung ,  Jae-Cheon Doh

Inventor： Ye-Chung Chung ,  Jae-Cheon Doh

IPC: B05D5/12

CPC classification number: B32B3/266 ,  H01L23/49833 ,  H01L23/4985 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

Abstract: The following invention is directed to a tape substrate having a reinforcement layer for tape packages and a method of fabricating the same. In an example embodiment, a tape substrate for tape packages may include a base film, a circuit pattern formed on the base film, and at least one reinforcement layer formed over a surface of the base film. The base film may have sprocket holes formed at regular intervals in the surface of the base film along at least one outer edge of the base film. The at least one reinforcement layer may have guide holes corresponding to the sprocket holes of the base film that are larger than the sprocket holes. The example embodiment may also include at least one reinforcement being set back from the outer edge of the base film.

Abstract translation: 以下发明涉及具有带包装用增强层的带基材及其制造方法。 在一个示例性实施例中，用于带包装的带基底可以包括基膜，形成在基膜上的电路图案，以及形成在基膜表面上的至少一个加强层。 基膜可以具有沿着基膜的至少一个外边缘在基膜的表面中以规则间隔形成的链轮孔。 所述至少一个加强层可以具有与所述基膜的链轮孔相对应的导引孔，所述引导孔大于所述链轮孔。 示例实施例还可以包括从基膜的外边缘回退的至少一个加强件。

公开(公告)号：US20070042166A1

公开(公告)日：2007-02-22

申请号：US11372115

申请日：2006-03-10

Applicant: Ye-Chung Chung ,  Jae-Cheon Doh

Inventor： Ye-Chung Chung ,  Jae-Cheon Doh

IPC: B32B15/00

CPC classification number: B32B3/266 ,  H01L23/49833 ,  H01L23/4985 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

Abstract: The following invention is directed to a tape substrate having a reinforcement layer for tape packages and a method of fabricating the same. In an example embodiment, a tape substrate for tape packages may include a base film, a circuit pattern formed on the base film, and at least one reinforcement layer formed over a surface of the base film. The base film may have sprocket holes formed at regular intervals in the surface of the base film along at least one outer edge of the base film. The at least one reinforcement layer may have guide holes corresponding to the sprocket holes of the base film that are larger than the sprocket holes. The example embodiment may also include at least one reinforcement being set back from the outer edge of the base film.

Abstract translation: 以下发明涉及具有带包装用增强层的带基材及其制造方法。 在一个示例性实施例中，用于带包装的带基底可以包括基膜，形成在基膜上的电路图案，以及形成在基膜表面上的至少一个加强层。 基膜可以具有沿着基膜的至少一个外边缘在基膜的表面中以规则间隔形成的链轮孔。 所述至少一个加强层可以具有与所述基膜的链轮孔相对应的导引孔，所述引导孔大于所述链轮孔。 示例实施例还可以包括从基膜的外边缘回退的至少一个加强件。

公开(公告)号：US20120162931A1

公开(公告)日：2012-06-28

申请号：US13177270

申请日：2011-07-06

Applicant: Tae Hoon Kim ,  Jae Cheon Doh ,  Seog Moon Choi

Inventor： Tae Hoon Kim ,  Jae Cheon Doh ,  Seog Moon Choi

IPC: H05K7/00

CPC classification number: H01L23/3121 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49575 ,  H01L25/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed herein is a 3D power module package, including: a power converting unit packaged to include a heat radiating substrate, a power device connected to the heat radiating substrate, and a lead frame; a controlling unit packaged to include a controlling unit substrate and IC and controlling devices mounted on an upper portion of the controlling unit substrate; and an electrical connecting unit electrically connecting the packaged power converting unit and the packaged controlling unit.

Abstract translation: 本文公开了一种3D功率模块封装，包括：封装成包括散热基板的功率转换单元，连接到散热基板的功率器件和引线框架; 控制单元，其被封装成包括控制单元基板和IC以及安装在所述控制单元基板的上部的控制装置; 以及电连接单元，电连接所述封装的电力转换单元和所述封装的控制单元。

公开(公告)号：US20110128011A1

公开(公告)日：2011-06-02

申请号：US12716948

申请日：2010-03-03

Applicant: Seung Seoup LEE ,  Jae Cheon Doh ,  In Kyung Park

Inventor： Seung Seoup LEE ,  Jae Cheon Doh ,  In Kyung Park

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/309

Abstract: Disclosed herein is an apparatus and method for inspecting defects in a circuit pattern. In the inspection apparatus and method, a laser beam is radiated by a laser unit onto a first end of a circuit pattern, and variation in impedance of a capacitor sensor disposed at a second end of the circuit pattern is measured, thus measuring the open/short circuits of the circuit pattern.Accordingly, the inspection apparatus and method are advantageous in that defects in the circuit pattern can be measured in a non-contact manner, so that the consumption of pin probes can be reduced, and the reliability of the measurement of defects in the circuit pattern can be improved.

Abstract translation: 本文公开了一种用于检查电路图案中的缺陷的装置和方法。 在检查装置和方法中，通过激光单元将激光束照射到电路图案的第一端，并且测量设置在电路图案的第二端的电容器传感器的阻抗的变化，从而测量开路/ 电路图案短路。 因此，检查装置和方法的优点在于，可以以非接触的方式测量电路图案的缺陷，从而可以减少引脚探针的消耗，并且电路图案中的缺陷的测量的可靠性可以 要改进