Iridium encased metal interconnects for integrated circuit applications
    5.
    发明申请
    Iridium encased metal interconnects for integrated circuit applications 审中-公开
    铱壳金属互连用于集成电路应用

    公开(公告)号:US20080045013A1

    公开(公告)日:2008-02-21

    申请号:US11506358

    申请日:2006-08-18

    IPC分类号: H01L21/44

    摘要: An iridium encased copper interconnect comprises an iridium liner formed within a trench in a dielectric layer, wherein the iridium liner is formed directly on the dielectric layer, a copper interconnect formed on the iridium liner, and an iridium capping layer formed on the copper interconnect. The iridium encased copper interconnect may be fabricated by providing a semiconductor substrate in a reactor, wherein the semiconductor substrate includes a trench etched into a dielectric layer, pulsing trimethylaluminum into the reactor proximate to the semiconductor substrate, pulsing an iridium precursor into the reactor proximate to the semiconductor substrate, wherein the trimethylaluminum enables an iridium species to deposit directly on the dielectric layer, depositing a copper seed layer on the iridium species layer using an electroless deposition process, and depositing a bulk copper layer on the copper seed layer using an electroplating process.

    摘要翻译: 铱包裹的铜互连包括形成在电介质层的沟槽内的铱衬里,其中铱衬垫直接形成在电介质层上,形成在铱衬垫上的铜互连以及形成在铜互连上的铱覆盖层。 可以通过在反应器中提供半导体衬底来制造铱包络铜互连,其中半导体衬底包括蚀刻到电介质层中的沟槽,将靠近半导体衬底的三甲基铝脉冲发射到反应器中,将铱前驱物脉冲至接近于 所述半导体衬底,其中所述三甲基铝能够使铱物质直接沉积在所述电介质层上,使用无电沉积工艺在所述铱物质层上沉积铜籽晶层,并且使用电镀工艺在所述铜籽晶层上沉积大块铜层 。

    Tunable gate electrode work function material for transistor applications
    6.
    发明授权
    Tunable gate electrode work function material for transistor applications 有权
    晶体管应用的可调栅电极功能材料

    公开(公告)号:US08319287B2

    公开(公告)日:2012-11-27

    申请号:US12705248

    申请日:2010-02-12

    IPC分类号: H01L29/78

    摘要: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.

    摘要翻译: 这里描述的金属栅极电极堆叠包括与金属碳氮化物扩散阻挡层接触的低电阻金属帽,其中金属碳氮化物扩散阻挡层被调谐到特定的功函数,以用作pMOS晶体管的功函数金属。 在一个实施例中,工作功能调谐金属碳氮化物扩散屏障禁止栅电极堆叠的低电阻金属盖层迁移到MOS结。 在本发明的另一个实施方案中,金属碳氮化物阻挡膜的功函数通过改变膜中的氮浓度而被调制为具有预选功函的p型。

    TUNABLE GATE ELECTRODE WORK FUNCTION MATERIAL FOR TRANSISTOR APPLICATIONS
    8.
    发明申请
    TUNABLE GATE ELECTRODE WORK FUNCTION MATERIAL FOR TRANSISTOR APPLICATIONS 有权
    用于晶体管应用的可控栅极电极功能材料

    公开(公告)号:US20100140717A1

    公开(公告)日:2010-06-10

    申请号:US12705248

    申请日:2010-02-12

    IPC分类号: H01L27/092

    摘要: Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.

    摘要翻译: 这里描述的金属栅极电极堆叠包括与金属碳氮化物扩散阻挡层接触的低电阻金属帽,其中金属碳氮化物扩散阻挡层被调谐到特定的功函数,以用作pMOS晶体管的功函数金属。 在一个实施例中,工作功能调谐金属碳氮化物扩散屏障禁止栅电极堆叠的低电阻金属盖层迁移到MOS结。 在本发明的另一个实施方案中,金属碳氮化物阻挡膜的功函数通过改变膜中的氮浓度而被调制为具有预选功函的p型。