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17 条记录 (耗时 0.042 秒)

    Semiconductor diffusion type force sensing apparatus
    1.
    发明授权
    Semiconductor diffusion type force sensing apparatus 失效
    半导体扩散型力传感装置

    公开(公告)号：US4884051A

    公开(公告)日：1989-11-28

    申请号：US215412

    申请日：1988-07-05

    申请人： Junichi Takahashi ,  Daisuke Kosaka ,  Hirotoshi Eguchi ,  Shoji Matsumoto ,  Takashi Akahori ,  Hiroshi Yamazaki ,  Kouji Izumi

    发明人： Junichi Takahashi ,  Daisuke Kosaka ,  Hirotoshi Eguchi ,  Shoji Matsumoto ,  Takashi Akahori ,  Hiroshi Yamazaki ,  Kouji Izumi

    IPC分类号： G01L1/18 ,  G01L5/16 ,  H01L41/04

    CPC分类号： G01L5/162 ,  G01L1/18

    摘要： A semiconductor diffusion type force sensing apparatus includes a plate-like semiconductor substrate formed by a single crystal material, and a plurality of sensing elements each constituted by a substantially rectangular impurity-diffused region formed in the semiconductor substrate. The sensing elements have an electric resistance variable in accordance with a deformation thereof due to an external force exerted on the semiconductor substrate. The sensing elements are arranged in a direction in which a longitudinal direction of each of the sensing elements coincides with a crystal orientation of the semiconductor substrate having an external value of a longitudinal piezoresistance coefficient of the impurity-diffused region.

    摘要翻译： 半导体扩散型力感测装置包括由单晶材料形成的板状半导体衬底和多个感测元件，每个感测元件由形成在半导体衬底中的大致矩形的杂质扩散区域构成。 感测元件由于施加在半导体衬底上的外力而具有根据其变形而变化的电阻。 感测元件布置在每个感测元件的纵向方向与具有杂质扩散区域的纵向压阻系数的外部值的半导体衬底的晶体取向一致的方向上布置。

    Thermal head
    2.
    发明授权
    Thermal head 失效
    热头

    公开(公告)号：US5041847A

    公开(公告)日：1991-08-20

    申请号：US570397

    申请日：1990-08-21

    申请人： Shoji Matsumoto ,  Daisuke Kosaka ,  Masaaki Yoshida ,  Hidehito Kitakado ,  Kenji Fujita

    发明人： Shoji Matsumoto ,  Daisuke Kosaka ,  Masaaki Yoshida ,  Hidehito Kitakado ,  Kenji Fujita

    IPC分类号： B41J2/335

    CPC分类号： B41J2/3353 ,  B41J2/33535 ,  B41J2/3355 ,  B41J2/3357

    摘要： A thermal head comprising a substrate, a heat-resistant dielectric resin layer disposed on the substrate, a resistor layer disposed on the resin layer for forming a plurality of heating elements and an electrode layer disposed on the resistor layer for forming electrodes connecting to the heating elements. A protection film covers an end of the substrate and each end of the layers which is substantially in the same plane as the substrate end.

    摘要翻译： 一种热敏头，包括基底，设置在基底上的耐热电介质树脂层，设置在用于形成多个加热元件的树脂层上的电阻层和设置在电阻层上的电极层，用于形成连接到加热的电极 元素。 保护膜覆盖基板的端部，并且层的每个端部基本上在与基板端部相同的平面中。

    Sense amplifier for a ROM having a multilevel memory cell
    6.
    发明授权
    Sense amplifier for a ROM having a multilevel memory cell 失效
    具有多电平存储单元的ROM的感测放大器

    公开(公告)号：US5012448A

    公开(公告)日：1991-04-30

    申请号：US220976

    申请日：1988-07-15

    申请人： Shigeki Matsuoka ,  Hiizu Okubo ,  Daisuke Kosaka

    发明人： Shigeki Matsuoka ,  Hiizu Okubo ,  Daisuke Kosaka

    IPC分类号： G11C7/14 ,  G11C11/56 ,  G11C16/28 ,  H01L27/112

    CPC分类号： G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5692 ,  G11C16/28 ,  G11C7/14 ,  H01L27/112 ,  G11C2211/5634 ,  G11C7/06

    摘要： A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying states and the other of which has the other current carrying state. A first current supplying circuit is connected to the memory MOSFET for supplying a predetermined amount of current thereto when the memory MOSFET is activated. A second current supplying circuit is connected to the pair of reference MOSFETs and also to the first current supplying circuit, such that twice the aforementioned predetermined amount of current is supplied to the pair of reference MOSFETs when the memory MOSFET is activated. A multilevel semiconductor memory device includes a MOSFET having a channel whose width is varyingly set by providing a non-inverting region in a selected area of the channel by ion implantation.

    摘要翻译： 多电平检测电路包括具有至少两个不同载流状态中的一个的存储器MOSFET和一对参考MOSFET，其中一个参考MOSFET具有两个载流状态之一，另一个具有另一个载流状态。 当存储器MOSFET被激活时，第一电流供应电路连接到存储器MOSFET，用于向其提供预定量的电流。 第二电流供应电路连接到一对参考MOSFET并且还连接到第一电流供应电路，使得当存储器MOSFET被激活时，上述预定量的电流被提供给一对参考MOSFET。 多级半导体存储器件包括MOSFET，其具有通过离子注入在沟道的选定区域中提供非反相区域而使宽度变化地设定的沟道。

    Method of manufacturing a semiconductor integrated circuit device having SOI structure
    9.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device having SOI structure 失效
    具有SOI结构的半导体集成电路器件的制造方法

    公开(公告)号：US5077235A

    公开(公告)日：1991-12-31

    申请号：US466059

    申请日：1990-01-16

    申请人： Daisuke Kosaka

    发明人： Daisuke Kosaka

    IPC分类号： H01L21/20 ,  H01L21/268 ,  H01L21/762

    CPC分类号： H01L21/76248 ,  H01L21/2026 ,  H01L21/268 ,  Y10S148/152

    摘要： A method of manufacturing a semiconductor integrated circuit device having a SOI structure includes the following steps. The first step is to form a semiconductor layer on a dielectric substrate. The second step is to form an oxide layer on the formed semiconductor layer. The third step is to form a nitride layer on the formed oxide layer. The fourth step is to remove a part of a plurality of layers composed of the semiconductor layer, the oxide layer, and a nitride layer so as to form a separated region in the layers. The fifth step is to coat a cooling agent on a surface of the nitride layer. The sixth step is to irradiate an energy beam from an outer surface of the cooling agent so as to monocrystallize the semiconductor layer. The seventh step is to remove the cooling agent from the surface of the nitride layer. And the final step is to oxidize a portion of the semiconductor layer located in the separated region by using the nitride layer. A semiconductor integrated circuit device having a SOI structure includes a semiconductor layer formed on a dielectric substrate, an oxide film formed on the semiconductor layer, a nitride layer formed on the oxide film, and a monocrystallized and oxidized semiconductor layer formed in hole portions formed in the semiconductor layer passing through the oxide layer and the nitride layer.

    摘要翻译： 制造具有SOI结构的半导体集成电路器件的方法包括以下步骤。 第一步是在电介质基板上形成半导体层。 第二步是在形成的半导体层上形成氧化物层。 第三步是在所形成的氧化物层上形成氮化物层。 第四步骤是去除由半导体层，氧化物层和氮化物层组成的多个层的一部分，以在层中形成分离的区域。 第五步是在氮化物层的表面上涂覆冷却剂。 第六步是从冷却剂的外表面照射能量束，以使半导体层单晶化。 第七步骤是从氮化物层的表面除去冷却剂。 最后一步是通过使用氮化物层来氧化位于分离区域中的半导体层的一部分。 具有SOI结构的半导体集成电路器件包括形成在电介质基板上的半导体层，形成在半导体层上的氧化膜，形成在氧化物膜上的氮化物层，以及形成在孔部中的单晶氧化半导体层 半导体层通过氧化物层和氮化物层。