公开(公告)号：US20150069634A1

公开(公告)日：2015-03-12

申请号：US14194783

申请日：2014-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yukifumi OYAMA ,  Hideko MUKAIDA ,  Masatoshi FUKUDA ,  Satoshi TSUKIYAMA ,  Shinya FUKAYAMA

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3135 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/15311

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip.

Abstract translation: 根据一个实施例，半导体器件包括具有第一主表面和第二主表面的第一半导体芯片，第一主表面和第二主表面相对于第一主表面并且第一电极安装在其上，第二半导体芯片具有第三主表面， 设置连接到第一电极的第二电极和与第三主表面相对的第四主表面和布置在形成在第一和第二电极之间的区域中的第一间隔件和第一和第二半导体芯片的外周表面 并且确保第一半导体芯片和第二半导体芯片之间的间隙。

公开(公告)号：US20150069110A1

公开(公告)日：2015-03-12

申请号：US14188517

申请日：2014-02-24

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya FUKAYAMA ,  Yukifumi OYAMA ,  Satoshi TSUKIYAMA ,  Masatoshi FUKUDA

IPC: H01L21/683 ,  B23K37/04 ,  B23K3/00

CPC classification number: H01L21/6838 ,  H01L21/677 ,  H01L24/75 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/7565 ,  H01L2224/81191

Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.

Abstract translation: 一种半导体制造装置，包括：吸收具有形成有凸块的主面的半导体芯片的夹头和通过驱动夹头将吸引的半导体芯片传送到安装基板或其他半导体芯片的致动器。 在吸收半导体芯片的夹头的吸附面上形成有用于避免夹头和凸块之间的接触的凹部。

公开(公告)号：US20160351541A1

公开(公告)日：2016-12-01

申请号：US15061989

申请日：2016-03-04

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya FUKAYAMA ,  Yukifumi OYAMA ,  Keisuke TANIGUCHI

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14152 ,  H01L2224/14177 ,  H01L2224/14181 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16146 ,  H01L2224/16238 ,  H01L2224/75315 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1438 ,  H01L2924/14511 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor device includes a semiconductor chip in which a first bump is provided on a first surface, a plurality of first adhesives are provided on the first surface of the semiconductor chip, and a second adhesive is provided on the first surface of the semiconductor chip, and of which a layout area on the first surface is smaller than a layout area of the plurality of first adhesives. In comparison to a first adhesive that is farthest from the center or a moment of inertia of the first surface of the semiconductor chip among the plurality of the first adhesives, the second adhesive is provided farther from the center or the moment of inertia of the semiconductor chip.

Abstract translation: 半导体器件包括：半导体芯片，其中第一凸起设置在第一表面上，多个第一粘合剂设置在半导体芯片的第一表面上，第二粘合剂设置在半导体芯片的第一表面上， 并且其第一表面上的布局面积小于多个第一粘合剂的布局面积。 与多个第一粘合剂中的距离半导体芯片的第一表面的中心或惯性矩最远的第一粘合剂相比，第二粘合剂被设置为远离半导体的中心或惯性矩 芯片。

公开(公告)号：US20160111317A1

公开(公告)日：2016-04-21

申请号：US14980317

申请日：2015-12-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya FUKAYAMA ,  Yukifumi OYAMA ,  Satoshi TSUKIYAMA ,  Masatoshi FUKUDA

IPC: H01L21/683 ,  H01L21/677 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/6838 ,  H01L21/677 ,  H01L24/75 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/7565 ,  H01L2224/81191

Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.

公开(公告)号：US20160079102A1

公开(公告)日：2016-03-17

申请号：US14636081

申请日：2015-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya FUKAYAMA ,  Yukifumi OYAMA ,  Kazuhiro MURAKAMI

IPC: H01L21/67 ,  H01L25/00 ,  G01B11/26 ,  H01L23/00 ,  H01L21/66 ,  H01L21/683 ,  H01L23/544 ,  H01L25/065

CPC classification number: G01B11/26 ,  G01B11/272 ,  G08B21/086 ,  H01L21/681 ,  H01L22/20 ,  H01L23/544 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/16145 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75804 ,  H01L2224/75901 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/8116 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81205 ,  H01L2224/81908 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/00014

Abstract: A method for manufacturing a semiconductor device includes determining a position of a first semiconductor chip having a plurality of first electrodes, using one or more first alignment marks formed on the first semiconductor chip, determining a position of a second semiconductor chip having a plurality of second electrodes, using one or more second alignment marks formed on the second semiconductor chip, moving the second semiconductor chip relative to the first semiconductor chip, based on the determined positions of the first and second semiconductor chips, such that the second electrodes are aligned with the first electrodes, after said moving, stacking the second semiconductor chip on the first semiconductor chip, such that the first electrodes are electrically connected to the second electrodes, and calculating a misalignment amount between the first semiconductor chip and the second semiconductor chip stacked thereon.

Abstract translation: 一种制造半导体器件的方法包括：使用形成在第一半导体芯片上的一个或多个第一对准标记来确定具有多个第一电极的第一半导体芯片的位置，确定具有多个第二电极的第二半导体芯片的位置 电极，使用形成在第二半导体芯片上的一个或多个第二对准标记，基于确定的第一和第二半导体芯片的位置，使第二半导体芯片相对于第一半导体芯片移动，使得第二电极与 第一电极，在所述移动之后，将第二半导体芯片堆叠在第一半导体芯片上，使得第一电极电连接到第二电极，并计算第一半导体芯片和堆叠在其上的第二半导体芯片之间的未对准量。

公开(公告)号：US20150123270A1

公开(公告)日：2015-05-07

申请号：US14474686

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TSUKIYAMA ,  Masatoshi FUKUDA ,  Yukifumi OYAMA ,  Shinya FUKAYAMA

IPC: H01L23/00 ,  H01L25/07 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/074 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/10135 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/1705 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Abstract translation: 根据一个实施例，第一电极形成在第一半导体芯片的第一面上，第二电极和突起形成在第二半导体芯片的第二面上。 第一半导体芯片和第二半导体芯片通过突起彼此间隔开，使得第一面和第二面彼此面对。 第一半导体芯片和第二半导体芯片经受回流以彼此电连接，然后突起在低于回流温度的温度下固化。