公开(公告)号：US20140206144A1

公开(公告)日：2014-07-24

申请号：US14221838

申请日：2014-03-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TSUKIYAMA ,  Masatoshi FUKUDA ,  Hiroshi WATABE ,  Keita MIZOGUCHI ,  Naoyuki KOMUTA

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14151 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/83104 ,  H01L2224/83815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00

Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips.

Abstract translation: 在一个实施例中，半导体器件包括堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片。 第一和第二半导体芯片通过第一凸块连接部电连接。 止动器突起和接合突起设置在第一和第二半导体芯片中的至少一个上。 止动突起与未粘合状态的第一和第二半导体芯片中的另一个接触。 接合突起接合到第一和第二半导体芯片。

公开(公告)号：US20160276290A1

公开(公告)日：2016-09-22

申请号：US15169246

申请日：2016-05-31

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Keiju YAMADA ,  Takashi YAMAZAKI ,  Masatoshi FUKUDA ,  Yasuhiro KOSHIO

IPC: H01L23/552 ,  H01L23/498 ,  H01L23/544 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: According to an embodiment, a semiconductor package includes a semiconductor chip mounted on an interposer board, a encapsulant sealing the semiconductor chip, and a conductive shielding layer covering the encapsulant and at least part of a side surface of the interposer board. The interposer board has plural vias through an insulating substrate. A part of the plural vias has a cutting plane exposing to the side surface of the interposer board and cut in a thickness direction of the interposer board. The cutting plane of the via is electrically connected to the conductive shielding layer.

Abstract translation: 根据实施例，半导体封装包括安装在插入板上的半导体芯片，密封半导体芯片的密封剂以及覆盖密封剂的导电屏蔽层和插入板的侧表面的至少一部分。 插入板具有通过绝缘基板的多个通路。 多个通孔的一部分具有暴露于插入板的侧表面并在插入板的厚度方向上切割的切割平面。 通孔的切割平面电连接到导电屏蔽层。

公开(公告)号：US20150069634A1

公开(公告)日：2015-03-12

申请号：US14194783

申请日：2014-03-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yukifumi OYAMA ,  Hideko MUKAIDA ,  Masatoshi FUKUDA ,  Satoshi TSUKIYAMA ,  Shinya FUKAYAMA

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L23/3135 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/15311

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor chip having a first main surface and a second main surface which opposes the first main surface and on which a first electrode is mounted, a second semiconductor chip having a third main surface on which a second electrode connected to the first electrode is provided and a fourth main surface which opposes the third main surface, and a first spacer which is arranged in a region formed between the first and second electrodes and an outer peripheral surface of the first and second semiconductor chips, and ensures a gap between the first semiconductor chip and the second semiconductor chip.

Abstract translation: 根据一个实施例，半导体器件包括具有第一主表面和第二主表面的第一半导体芯片，第一主表面和第二主表面相对于第一主表面并且第一电极安装在其上，第二半导体芯片具有第三主表面， 设置连接到第一电极的第二电极和与第三主表面相对的第四主表面和布置在形成在第一和第二电极之间的区域中的第一间隔件和第一和第二半导体芯片的外周表面 并且确保第一半导体芯片和第二半导体芯片之间的间隙。

公开(公告)号：US20150069110A1

公开(公告)日：2015-03-12

申请号：US14188517

申请日：2014-02-24

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya FUKAYAMA ,  Yukifumi OYAMA ,  Satoshi TSUKIYAMA ,  Masatoshi FUKUDA

IPC: H01L21/683 ,  B23K37/04 ,  B23K3/00

CPC classification number: H01L21/6838 ,  H01L21/677 ,  H01L24/75 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/7565 ,  H01L2224/81191

Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.

Abstract translation: 一种半导体制造装置，包括：吸收具有形成有凸块的主面的半导体芯片的夹头和通过驱动夹头将吸引的半导体芯片传送到安装基板或其他半导体芯片的致动器。 在吸收半导体芯片的夹头的吸附面上形成有用于避免夹头和凸块之间的接触的凹部。

公开(公告)号：US20170263582A1

公开(公告)日：2017-09-14

申请号：US15252139

申请日：2016-08-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeori MAEDA ,  Masatoshi FUKUDA ,  Ryoji MATSUSHIMA ,  Hideo AOKI

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/56 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/14133 ,  H01L2224/14505 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/0635

Abstract: A semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first and second semiconductor elements and electrically connects the first and second semiconductor elements. The bonding portion is between the first and second semiconductor elements, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. The resin portion is between the first and second semiconductor elements. The first semiconductor element is between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first and second semiconductor elements.

公开(公告)号：US20140284817A1

公开(公告)日：2014-09-25

申请号：US14015027

申请日：2013-08-30

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takao SATO ,  Masatoshi FUKUDA

IPC: H01L25/00 ,  H01L25/07

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/18 ,  H01L2223/54453 ,  H01L2223/54486 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/32225 ,  H01L2224/81065 ,  H01L2224/81132 ,  H01L2224/81815 ,  H01L2224/81907 ,  H01L2224/83132 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/00012

Abstract: According to one embodiment a method is provided including positioning and bonding a plurality of first semiconductor chips in a coplanar relation on a first substrate, laminating at least a plurality of second semiconductor chips on the first semiconductor chips, cutting the first substrate for separation into a discrete chip lamination, aligning an electrode pad provided on a surface of the discrete lamination with an electrode pad on a second substrate, and temporarily connecting the electrode pads on the lamination and the second substrate in an opposing relation to the first substrate, providing electrical connection between the electrode pads by a reflow process, flowing a liquid resin from the side of the first substrate towards the second substrate to seal the chip lamination and spaces between the chip lamination and the first and second substrate, and cutting the chip lamination to form a discrete device.

Abstract translation: 根据一个实施例，提供了一种方法，包括在第一基板上定位并结合共面关系中的多个第一半导体芯片，在第一半导体芯片上层叠至少多个第二半导体芯片，将第一基板切割成 离散芯片层叠，将设置在分立层叠体的表面上的电极焊盘与第二衬底上的电极焊盘对准，并且以与第一衬底相对的关系临时连接层压体和第二衬底上的电极焊盘，从而提供电连接 通过回流工艺在电极焊盘之间，将液态树脂从第一衬底的侧面朝向第二衬底流动，以密封芯片层叠和芯片层压体与第一和第二衬底之间的间隔，并且切割芯片层叠以形成 离散设备。

公开(公告)号：US20160111317A1

公开(公告)日：2016-04-21

申请号：US14980317

申请日：2015-12-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinya FUKAYAMA ,  Yukifumi OYAMA ,  Satoshi TSUKIYAMA ,  Masatoshi FUKUDA

IPC: H01L21/683 ,  H01L21/677 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/6838 ,  H01L21/677 ,  H01L24/75 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/7565 ,  H01L2224/81191

Abstract: A semiconductor manufacturing apparatus includes: a collet which sucks a semiconductor chip having a main surface on which a bump is formed, and an actuator which transfers the sucked semiconductor chip onto a mounting substrate or another semiconductor chip by driving the collet. A recessed portion for avoiding a contact between the collet and the bump is formed on a suction surface of the collet which sucks the semiconductor chip.

公开(公告)号：US20150123270A1

公开(公告)日：2015-05-07

申请号：US14474686

申请日：2014-09-02

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Satoshi TSUKIYAMA ,  Masatoshi FUKUDA ,  Yukifumi OYAMA ,  Shinya FUKAYAMA

IPC: H01L23/00 ,  H01L25/07 ,  H01L23/544 ,  H01L25/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/544 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L25/074 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/10135 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/1403 ,  H01L2224/1415 ,  H01L2224/14505 ,  H01L2224/16146 ,  H01L2224/1705 ,  H01L2224/17517 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81139 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81862 ,  H01L2224/81907 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/35 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2224/8185 ,  H01L2924/0665 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.

Abstract translation: 根据一个实施例，第一电极形成在第一半导体芯片的第一面上，第二电极和突起形成在第二半导体芯片的第二面上。 第一半导体芯片和第二半导体芯片通过突起彼此间隔开，使得第一面和第二面彼此面对。 第一半导体芯片和第二半导体芯片经受回流以彼此电连接，然后突起在低于回流温度的温度下固化。