公开(公告)号：US08624360B2

公开(公告)日：2014-01-07

申请号：US12616562

申请日：2009-11-11

申请人： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming-Hong Tseng ,  Chen-Shien Chen

发明人： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming-Hong Tseng ,  Chen-Shien Chen

IPC分类号： H01L29/40 ,  H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

摘要翻译： 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。 多个通道被配置成允许流体流过。

公开(公告)号：US20100102453A1

公开(公告)日：2010-04-29

申请号：US12259879

申请日：2008-10-28

申请人： Ming-Hong Tseng ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Hon-Lin Huang ,  Tsung-Ding Wang

发明人： Ming-Hong Tseng ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Hon-Lin Huang ,  Tsung-Ding Wang

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00

摘要： A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.

摘要翻译： 提出了一种制造叠层半导体衬底的系统，结构和方法。 第一基板包括第一侧和第二侧。 贯穿基板通孔（TSV）从第一基板的第一侧突出。 TSV的第一突出部分具有导电保护涂层，并且TSV的第二突出部分具有隔离衬垫。 该系统还包括在TSV的第一突出部分的导电保护涂层处将第二衬底与第一衬底结合的第二衬底和接合界面结构。

公开(公告)号：US20100117201A1

公开(公告)日：2010-05-13

申请号：US12616562

申请日：2009-11-11

申请人： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming-Hong Tseng ,  Chen-Shien Chen

发明人： Kai-Ming Ching ,  Ching-Wen Hsiao ,  Tsung-Ding Wang ,  Ming-Hong Tseng ,  Chen-Shien Chen

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L25/0657 ,  H01L23/46 ,  H01L23/473 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5226 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.

摘要翻译： 集成电路结构包括：具有半导体衬底的裸片; 半导体衬底上的电介质层; 包括电介质层中的金属线和通孔的互连结构; 从所述半导体衬底的内部延伸到所述电介质层的内部的多个沟道; 以及在所述多个通道的互连结构和密封部分上的电介质膜。 多个通道被配置成允许流体流过。

公开(公告)号：US08097953B2

公开(公告)日：2012-01-17

申请号：US12259879

申请日：2008-10-28

申请人： Ming-Hong Tseng ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Hon-Lin Huang ,  Tsung-Ding Wang

发明人： Ming-Hong Tseng ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Ching-Wen Hsiao ,  Hon-Lin Huang ,  Tsung-Ding Wang

IPC分类号： H01L23/52

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/01019 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/00

摘要： A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.

摘要翻译： 提出了一种制造叠层半导体衬底的系统，结构和方法。 第一基板包括第一侧和第二侧。 贯穿基板通孔（TSV）从第一基板的第一侧突出。 TSV的第一突出部分具有导电保护涂层，并且TSV的第二突出部分具有隔离衬垫。 该系统还包括在TSV的第一突出部分的导电保护涂层处将第二衬底与第一衬底结合的第二衬底和接合界面结构。

公开(公告)号：US08426256B2

公开(公告)日：2013-04-23

申请号：US12700929

申请日：2010-02-05

申请人： C. W. Hsiao ,  Bo-I Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

发明人： C. W. Hsiao ,  Bo-I Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

IPC分类号： H01L21/00

CPC分类号： H01L23/3114 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/00

摘要： A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

摘要翻译： 公开了一种形成堆叠的模具结构的方法。 多个管芯分别与晶片的第一表面上的多个半导体芯片接合。 在多个管芯和晶片的第一表面上形成封装结构。 封装结构覆盖晶片的第一表面的中心部分并且使晶片的边缘部分露出。 在晶片的边缘部分的第一表面上形成保护材料。

公开(公告)号：US20100279463A1

公开(公告)日：2010-11-04

申请号：US12700929

申请日：2010-02-05

申请人： C. W. Hsiao ,  Bo-l Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

发明人： C. W. Hsiao ,  Bo-l Lee ,  Tsung-Ding Wang ,  Kai-Ming Ching ,  Chen-Shien Chen ,  Chien-Hsiun Lee ,  Clinton Chao

IPC分类号： H01L21/78 ,  H01L21/768 ,  H01L21/50 ,  H01L21/56

CPC分类号： H01L23/3114 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/00

摘要： A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

摘要翻译： 公开了一种形成堆叠的模具结构的方法。 多个管芯分别与晶片的第一表面上的多个半导体芯片接合。 在多个管芯和晶片的第一表面上形成封装结构。 封装结构覆盖晶片的第一表面的中心部分并且使晶片的边缘部分露出。 在晶片的边缘部分的第一表面上形成保护材料。

公开(公告)号：US07888236B2

公开(公告)日：2011-02-15

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分开的多个第二裸片的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。

公开(公告)号：US08932906B2

公开(公告)日：2015-01-13

申请号：US12193950

申请日：2008-08-19

申请人： Dean Wang ,  Chen-Shien Chen ,  Kai-Ming Ching ,  Bo-I Lee ,  Chien-Hsiun Lee

发明人： Dean Wang ,  Chen-Shien Chen ,  Kai-Ming Ching ,  Bo-I Lee ,  Chien-Hsiun Lee

IPC分类号： H01L21/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/18

CPC分类号： H01L25/0657 ,  H01L21/187 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16146 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/00014

摘要： System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

摘要翻译： 提出了用于接合半导体衬底的系统和方法。 优选实施例包括在半导体衬底的表面上形成缓冲层，同时保留从缓冲层突出的TSV，以便防止可能形成的潜在的空隙。 在与第一半导体衬底接合的另一个半导体衬底上形成保护层。 两个基板对准并结合在一起，缓冲层防止与原始半导体衬底的表面的任何短路接触。

公开(公告)号：US20080296763A1

公开(公告)日：2008-12-04

申请号：US11756347

申请日：2007-05-31

申请人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

发明人： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC分类号： H01L23/488

CPC分类号： H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

摘要翻译： 提供半导体管芯封装。 半导体管芯封装包括以堆叠构造布置的多个管芯。 在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。 下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。 堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。 堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。 此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。

公开(公告)号：US20080286938A1

公开(公告)日：2008-11-20

申请号：US11798432

申请日：2007-05-14

申请人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

发明人： Han-Ping Pu ,  Bai-Yao Lou ,  Dean Wang ,  Ching-Wen Hsiao ,  Kai-Ming Ching ,  Chen-Cheng Kuo ,  Wen-Chih Chiou ,  Ding-Chung Lu ,  Shang-Yun Hou

IPC分类号： H01L21/30

CPC分类号： H01L21/78 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/11 ,  H01L2924/00014

摘要： A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.

摘要翻译： 一种封装半导体器件的方法。 提供了包括分别由划线区域分隔的多个管芯的衬底，其中至少一层覆盖衬底。 通过光刻和蚀刻去除划线部分内的层的一部分以形成开口。 沿着划线区域锯切基板，通过开口。 在替代实施例中，提供了包括分别由第一划线区域分开的多个第一裸片的第一衬底，其中至少一个第一结构层覆盖在第一衬底上。 图案化第一结构层以在第一划线区域内形成第一开口。 提供了包括分别由第二划线区域分隔的多个第二模具的第二衬底，其中至少一个第二结构层覆盖在衬底上。 图案化第二结构层以在第二划线区域内形成第二开口。 第一基板和第二基板被接合以形成堆叠结构。 沿着第一和第二划线区域切割堆叠结构，使第一和第二开口通过。