公开(公告)号：US08217466B2

公开(公告)日：2012-07-10

申请号：US11990491

申请日：2006-08-01

申请人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

IPC分类号： H01L21/70

CPC分类号： H01L27/1211 ,  H01L21/823493 ,  H01L27/0705 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

摘要翻译： 公开了一种半导体器件，其中晶体管的开关速度增加。 具体公开了一种半导体器件，包括形成在绝缘层的一部分上的半导体层，形成在半导体层的侧面上的第一晶体管，并具有第一栅极绝缘膜，第一栅电极和两个第一杂质层， 源极和漏极，以及形成在所述半导体层的另一个侧面上并具有第二栅极绝缘膜，第二栅极电极和形成源极和漏极的两个第二杂质层的第二晶体管。

公开(公告)号：US20090096029A1

公开(公告)日：2009-04-16

申请号：US11990491

申请日：2006-08-01

申请人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Fumio Mizuno ,  Munekazu Takano ,  Tamotsu Usami

IPC分类号： H01L27/088 ,  H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/823493 ,  H01L27/0705 ,  H01L29/66795 ,  H01L29/785

摘要： Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

摘要翻译： 公开了一种半导体器件，其中晶体管的开关速度增加。 具体公开了一种半导体器件，包括形成在绝缘层的一部分上的半导体层，形成在半导体层的侧面上的第一晶体管，并具有第一栅极绝缘膜，第一栅电极和两个第一杂质层， 源极和漏极，以及形成在所述半导体层的另一个侧面上并具有第二栅极绝缘膜，第二栅极电极和形成源极和漏极的两个第二杂质层的第二晶体管。

公开(公告)号：US07631422B2

公开(公告)日：2009-12-15

申请号：US11440113

申请日：2006-05-25

申请人： Kanji Otsuka ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Tamotsu Usami

IPC分类号： H05K3/28 ,  H05K3/30 ,  H05K3/32

CPC分类号： H04L25/0298 ,  G06F13/4086 ,  H01L2224/32225 ,  H04L25/0266 ,  H05K1/024 ,  H05K1/0246 ,  H05K1/0306 ,  H05K1/167 ,  H05K3/284 ,  H05K2201/09672 ,  H05K2201/10022 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/49146

摘要： A terminal resistor is provided at the end of a bus formed on a wiring substrate. An insulator having a large dielectric loss angle is provided in the vicinity of the terminal resistor to absorb high frequency electromagnetic waves in the vicinity. This arrangement permits successful transmission of digital signals in the GHz region using a conventional terminal resistor.

摘要翻译： 端子电阻器设置在形成在布线基板上的总线的端部。 在端子电阻附近设置具有大的介电损耗角的绝缘体，以吸收附近的高频电磁波。 这种布置允许使用传统的终端电阻器在GHz区域成功传输数字信号。

公开(公告)号：US07446567B2

公开(公告)日：2008-11-04

申请号：US10775223

申请日：2004-02-11

申请人： Kanji Otsuka ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Tamotsu Usami

IPC分类号： H03K17/16 ,  H03K19/094

CPC分类号： H04L5/1461

摘要： Apparatus for transmitting a digital signal within, for example, an integrated circuit includes a signal transmission line with a directional coupler at one or both ends. The directional coupler blocks the direct-current component of the digital signal while transmitting the alternating-current component, including enough higher harmonics to transmit a well-defined pulse waveform. A suitable directional coupler consists of two adjacent line pairs in materials with different dielectric constants. The apparatus may also include a driver of the inverter type, a receiver of the differential amplifier type, a terminating resistor, and a power-ground transmission line pair for supplying power to the driver. An all-metallic transmission-line structure is preferably maintained from the output interconnections in the driver to the input interconnections in the receiver.

摘要翻译： 在例如集成电路内发送数字信号的装置包括在一端或两端具有定向耦合器的信号传输线。 定向耦合器阻止数字信号的直流分量，同时传输交流分量，包括足够的高次谐波以传输明确定义的脉冲波形。 合适的定向耦合器由具有不同介电常数的材料中的两个相邻线对组成。 该装置还可以包括逆变器类型的驱动器，差分放大器类型的接收器，终端电阻器和用于向驱动器供电的电源 - 地线传输线对。 优选地，从驱动器中的输出互连到接收器中的输入互连，保持全金属传输线结构。

公开(公告)号：US07280385B2

公开(公告)日：2007-10-09

申请号：US11360681

申请日：2006-02-24

申请人： Kanji Otsuka ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Tamotsu Usami

IPC分类号： G11C11/24

CPC分类号： H01L27/108 ,  G11C5/063 ,  G11C7/12 ,  G11C7/18 ,  G11C11/405 ,  G11C11/4094 ,  G11C11/4097

摘要： A memory cell MC includes nMOS transistors for a transfer gate configured to be paired with each other, and one capacitor for data storage connected to the nMOS transistor. A gate electrode of the nMOS transistor is connected to a word line WL, and a drain is connected to a bit line BL. A gate electrode of the nMOS transistor is connected to a word line /WL, and a drain and a source are connected to a ground. The capacitor is connected between a source of the nMOS transistor and the ground. A Y selector circuit is connected between a differential bit line BL, /BL and a differential data line DL, /DL. The Y selector circuit has two pairs of nMOS transistors configured to be paired transistors, respectively.

摘要翻译： 存储单元MC包括用于被配置为彼此配对的传输门的nMOS晶体管，以及连接到nMOS晶体管的一个用于数据存储的电容器。 nMOS晶体管的栅电极连接到字线WL，漏极连接到位线BL。 nMOS晶体管的栅电极连接到字线/ WL，漏极和源极连接到地。 电容器连接在nMOS晶体管的源极和地之间。 Y选择电路连接在差分位线BL，/ BL和差分数据线DL / DL之间。 Y选择器电路具有分别配置为成对晶体管的两对nMOS晶体管。

公开(公告)号：US20050179465A1

公开(公告)日：2005-08-18

申请号：US10511720

申请日：2003-04-21

申请人： Kanji Otsuka ,  Tamotsu Usami ,  Tetsuya Higuchi ,  Eiichi Takahashi ,  Yuji Kasai ,  Masahiro Murakawa

发明人： Kanji Otsuka ,  Tamotsu Usami ,  Tetsuya Higuchi ,  Eiichi Takahashi ,  Yuji Kasai ,  Masahiro Murakawa

IPC分类号： H04B3/04 ,  H04L25/02 ,  G06F11/00

CPC分类号： H04B3/04 ,  H01L2224/48227 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19107 ,  H04L25/0286 ,  H01L2924/00

摘要： A purpose of a high-speed signal transmission system of the present invention is to pass a high-speed digital signal through an outside-chip line exchanging a signal with a high speed LSI chip with a band higher than GHz. The high-speed signal transmission system of the present invention has a configuration of: insertion of a circuit for feeding back received information and adjusting a waveform at a sending side based on genetic algorithm; a device structure for automatically performing pump up and pump down of a transistor carrier; a transmission line of a wiring out of a transistor; and elimination of a common power source of a circuit.

摘要翻译： 本发明的高速信号传输系统的目的是通过外部芯片线路将高速数字信号与具有高于GHz的频带的高速LSI芯片交换信号。 本发明的高速信号传输系统具有以下结构：基于遗传算法插入用于反馈接收信息的电路和调整发送侧的波形; 用于自动地执行泵浦和泵浦晶体管载体的装置结构; 晶体管的布线传输线; 并消除电路的公共电源。

公开(公告)号：US06625005B2

公开(公告)日：2003-09-23

申请号：US09900960

申请日：2001-07-10

申请人： Kanji Otsuka ,  Tamotsu Usami

发明人： Kanji Otsuka ,  Tamotsu Usami

IPC分类号： H01G400

CPC分类号： H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a semiconductor chip are arranged power pads, ground pads and signal pads. A ground line is provided which is formed as one in the vicinity of the chip and branches off at some distance from the chip. Signal lines and power lines are each formed over one of the branched ground lines. The signal lines and the power lines are extended radially together with the underlying ground lines. Each of the signal lines and the power lines are extended together with the corresponding ground line to form a stacked pair line.

公开(公告)号：US07872612B2

公开(公告)日：2011-01-18

申请号：US12155247

申请日：2008-05-30

申请人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Chihiro Ueda

发明人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Chihiro Ueda

IPC分类号： H01Q9/28

CPC分类号： H01Q13/06

摘要： An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.

摘要翻译： 利用连接到具有预定特性阻抗的第一传输线的传输线孔径的天线装置包括锥形线部分和开口部分。 锥形线部分连接到传输线的一端，并且锥形线部分包括包括一对线导体的第二传输线。 锥形线部分保持预定的特性阻抗恒定，并以预定的锥角将传输线的宽度和间隔的至少一个以锥形形状扩展。 开口部分具有连接到锥形线部分的一端的辐射孔。 开口部的孔径端面的一侧的尺寸被设定为等于或高于天线装置的最小工作频率的四分之一波长。

公开(公告)号：US07791852B2

公开(公告)日：2010-09-07

申请号：US11819579

申请日：2007-06-28

申请人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Tsuneo Ito ,  Yuko Tanba

发明人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Tsuneo Ito ,  Yuko Tanba

IPC分类号： H02H3/22

CPC分类号： H01L27/0266

摘要： Disclosed is an electrostatic discharge protection circuit capable of realizing speeding up of differential signals by reducing a capacitance of the circuit. Transmission lines are connected to an IN terminal and an IN Bar terminal and differential signals are input to the terminals. The ESD protection circuit is connected to the transmission lines and protects an internal circuit from a surge voltage applied to the IN terminal and the IN Bar terminal. A pair of transistors of the ESD protection circuit is formed in the same well. Thereby, when differential signals transit, charges in drains of the pair of transistors holding a state before a transition transfer in the same well. As a result, the capacitances in the drains of the pair of transistors are reduced with respect to the transition of differential signals so that the speeding up of differential signals can be realized.

摘要翻译： 公开了一种能够通过减小电路的电容来实现差分信号的加速的静电放电保护电路。 传输线连接到IN端子，IN条形端子和差分信号输入端子。 ESD保护电路连接到传输线，并保护内部电路免受施加到IN端子和IN Bar端子的浪涌电压。 ESD保护电路的一对晶体管形成在同一个阱中。 因此，当差分信号转移时，在同一井内转移转移之前保持状态的一对晶体管的漏极中的电荷。 结果，一对晶体管的漏极中的电容相对于差分信号的转变而减小，从而可以实现差分信号的加速。

公开(公告)号：US20080316136A1

公开(公告)日：2008-12-25

申请号：US12155247

申请日：2008-05-30

申请人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Chihiro Ueda

发明人： Kanji Otsuka ,  Tamotsu Usami ,  Yutaka Akiyama ,  Chihiro Ueda

IPC分类号： H01Q9/28

CPC分类号： H01Q13/06

摘要： An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus.

摘要翻译： 利用连接到具有预定特性阻抗的第一传输线的传输线孔径的天线装置包括锥形线部分和开口部分。 锥形线部分连接到传输线的一端，并且锥形线部分包括包括一对线导体的第二传输线。 锥形线部分保持预定的特性阻抗恒定，并以预定的锥角将传输线的宽度和间隔的至少一个以锥形形状扩展。 开口部分具有连接到锥形线部分的一端的辐射孔。 开口部的孔径端面的一侧的尺寸被设定为等于或高于天线装置的最小工作频率的四分之一波长。