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公开(公告)号：US07500306B2
公开(公告)日：2009-03-10
申请号：US10912257
申请日：2004-08-05
CPC分类号： H05K1/115 , H05K1/0268 , H05K3/4602 , H05K3/4623 , H05K2201/09518 , H05K2201/09536 , H05K2201/096 , H05K2203/162 , Y10T29/49004 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A method of forming an electrical structure that includes a complex power-signal (CPS) substructure. The CPS substructure is formed and tested to determine whether the CPS substructure satisfies electrical performance acceptance requirements. The testing includes testing for electrical shorts, electrical opens, erroneous impedances, and electrical signal delay. If the CPS substructure passes the testes, then a dielectric-metallic (DM) laminate is formed on an external surface of the CPS substructure. The DM laminate includes an alternating sequence of an equal number N of dielectric layers and metallic layers such that a first dielectric layer of the N dielectric layers is formed on an external surface of the CPS substructure. N is at least 2. A multilevel conductive via is formed through the DM laminate and is electrically coupled to a metal layer of the CPS substructure.
摘要翻译： 一种形成包括复合功率信号（CPS）子结构的电气结构的方法。 形成和测试CPS子结构以确定CPS子结构是否满足电气性能验收要求。 测试包括测试电气短路，电气开路，错误阻抗和电信号延迟。 如果CPS子结构通过睾丸，则在CPS子结构的外表面上形成介电金属（DM）层压体。 DM层压板包括相等数量的N个介电层和金属层的交替序列，使得N个介电层的第一介电层形成在CPS子结构的外表面上。 N至少为2.通过DM层压体形成多层导电通孔，并电耦合到CPS子结构的金属层。
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公开(公告)号：US06810583B2
公开(公告)日：2004-11-02
申请号：US09924204
申请日：2001-08-07
IPC分类号： H01K310
CPC分类号： H05K1/115 , H05K1/0268 , H05K3/4602 , H05K3/4623 , H05K2201/09518 , H05K2201/09536 , H05K2201/096 , H05K2203/162 , Y10T29/49004 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： An electrical structure that includes a complex power-signal (CPS) substructure. The CPS substructure is formed and tested to determine whether the CPS substructure satisfies electrical performance acceptance requirements. The testing includes testing for electrical shorts, electrical opens, erroneous impedances, and electrical signal delay. If the CPS substructure passes the tests, then a dielectric-metallic (DM) laminate is formed on an external surface of the CPS substructure. The DM laminate includes an alternating sequence of an equal number N of dielectric layers and metallic layers such that a first dielectric layer of the N dielectric layers is formed on an external surface of the CPS substructure. N is at least 2. A multilevel conductive via is formed through the DM laminate and is electrically coupled to a metal layer of the CPS substructure.
摘要翻译： 包括复合功率信号（CPS）子结构的电气结构。 形成和测试CPS子结构以确定CPS子结构是否满足电气性能验收要求。 测试包括测试电气短路，电气开路，错误阻抗和电信号延迟。 如果CPS子结构通过测试，则在CPS子结构的外表面上形成介电金属（DM）层压体。 DM层压板包括相等数量的N个介电层和金属层的交替序列，使得N个介电层的第一介电层形成在CPS子结构的外表面上。 N至少为2.通过DM层压体形成多层导电通孔，并电耦合到CPS子结构的金属层。
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公开(公告)号：US07176383B2
公开(公告)日：2007-02-13
申请号：US10740398
申请日：2003-12-22
IPC分类号： H05K1/03
CPC分类号： H05K1/0216 , H05K1/0228 , H05K2201/09236 , H05K2201/09672 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A printed circuit board and a method of making same in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.
摘要翻译： 一种印刷电路板及其制造方法，其中所述板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括多条基本上平行的信号线， 基本相似的方向跨越所述信号层。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。
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公开(公告)号：US07152319B2
公开(公告)日：2006-12-26
申请号：US10811817
申请日：2004-03-30
申请人： Benson Chan , John M. Lauffer , How T. Lin , Voya R. Markovich , David L. Thomas
发明人： Benson Chan , John M. Lauffer , How T. Lin , Voya R. Markovich , David L. Thomas
IPC分类号： H01K3/10
CPC分类号： H05K3/4688 , H01L23/3128 , H01L23/5383 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01019 , H01L2924/01046 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/16195 , H01L2924/3011 , H01L2924/3025 , H05K1/024 , H05K1/113 , H05K3/4623 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , Y10T29/49126 , Y10T29/49165 , H01L2224/0401
摘要： A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.
摘要翻译： 包括两个多层部分的多层PCB，其中之一能够电连接安装在PCB上的电子部件，以确保其间的高频连接。 PCB还包括常规PCB部分以降低成本，同时确保具有令人满意的整体厚度的结构以用于PCB领域。 这些组件的内部部分也可以进行耦合。 也提供了制造这些结构的方法。
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公开(公告)号：US06894228B2
公开(公告)日：2005-05-17
申请号：US10217674
申请日：2002-08-12
申请人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
发明人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
IPC分类号： H01L23/538 , H05K1/02 , H05K3/46
CPC分类号： H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/0263 , H05K1/0265 , H05K3/4602 , H05K3/4611 , H05K2201/0352 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , H05K2203/1581 , H01L2924/00
摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.
摘要翻译： 一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。 密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路 必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。 本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。
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公开(公告)号：US07530167B2
公开(公告)日：2009-05-12
申请号：US11634287
申请日：2006-12-06
IPC分类号： H01K3/10
CPC分类号： H05K1/0216 , H05K1/0228 , H05K2201/09236 , H05K2201/09672 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A method of making a printed circuit board in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.
摘要翻译： 一种制造印刷电路板的方法，其中所述基板包括在其相对侧上具有电介质层的公共电源平面和每个所述电介质层上的信号层，每个信号层包括基本相似的多条基本上平行的信号线 跨越所述信号层的方向。 一个信号层中的信号线的预定部分相对于并且平行于另一个信号层中的相应的信号线，而功率平面位于这些部分之间。 在两层中的选定信号线之间提供通孔连接，这些连接通过电源平面中的间隙而发生，从而与其隔离。
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7.发明申请Circuitized substrate with internal cooling structure and electrical assembly utilizing same 失效具有内部冷却结构的电路化基板和利用其的电气组件公开(公告)号：US20090109624A1
公开(公告)日：2009-04-30
申请号：US11976468
申请日：2007-10-25
申请人： Benson Chan , Frank D. Egitto , How T. Lin , Roy H. Magnuson , Voya R. Markovich , David L. Thomas
发明人： Benson Chan , Frank D. Egitto , How T. Lin , Roy H. Magnuson , Voya R. Markovich , David L. Thomas
CPC分类号： H05K1/0206 , H01L2924/0002 , H05K1/0272 , H05K3/0061 , H05K3/44 , H05K2201/064 , H05K2201/09745 , H05K2201/10674 , Y10S428/901 , Y10T29/49126 , Y10T29/4913 , Y10T428/24917 , H01L2924/00
摘要： An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided.
摘要翻译： 一种电气组件，其包括电路化衬底，其包括以层叠取向交替取向的第一多个电介质和导电电路层，结合到所述电介质层之一的热冷结构和安装在所述电路化衬底上的至少一个电气部件。 电路化衬底包括位于其中的多个导电和导热通孔，选择的导热通孔热耦合到电气部件并延伸穿过第一多个电介质和导电电路层，并且 热耦合到热冷却结构，这些选择的导热通孔中的每一个在组装操作期间提供从电气部件到热冷却结构的热路径。 热冷却结构适于在组件的操作期间使冷却流体通过。 还提供了制造基板的方法。
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8.发明授权Circuitized substrate with internal cooling structure and electrical assembly utilizing same 失效具有内部冷却结构的电路化基板和利用其的电气组件公开(公告)号：US07738249B2
公开(公告)日：2010-06-15
申请号：US11976468
申请日：2007-10-25
申请人： Benson Chan , Frank D. Egitto , How T. Lin , Roy H. Magnuson , Voya R. Markovich , David L. Thomas
发明人： Benson Chan , Frank D. Egitto , How T. Lin , Roy H. Magnuson , Voya R. Markovich , David L. Thomas
IPC分类号： H05K7/20
CPC分类号： H05K1/0206 , H01L2924/0002 , H05K1/0272 , H05K3/0061 , H05K3/44 , H05K2201/064 , H05K2201/09745 , H05K2201/10674 , Y10S428/901 , Y10T29/49126 , Y10T29/4913 , Y10T428/24917 , H01L2924/00
摘要： An electrical assembly which includes a circuitized substrate including a first plurality of dielectric and electrically conductive circuit layers alternatively oriented in a stacked orientation, a thermal cooling structure bonded to one of the dielectric layers and at least one electrical component mounted on the circuitized substrate. The circuitized substrate includes a plurality of electrically conductive and thermally conductive thru-holes located therein, selected ones of the thermally conductive thru-holes thermally coupled to the electrical component(s) and extending through the first plurality of dielectric and electrically conductive circuit layers and being thermally coupled to the thermal cooling structure, each of these selected ones of thermally conductive thru-holes providing a thermal path from the electrical component to the thermal cooling structure during assembly operation. The thermal cooling structure is adapted for having cooling fluid pass there-through during operation of the assembly. A method of making the substrate is also provided.
摘要翻译： 一种电气组件，其包括电路化衬底，其包括以层叠取向交替取向的第一多个电介质和导电电路层，结合到所述电介质层之一的热冷结构和安装在所述电路化衬底上的至少一个电气部件。 电路化衬底包括位于其中的多个导电和导热通孔，选择的导热通孔热耦合到电气部件并延伸穿过第一多个电介质和导电电路层，并且 热耦合到热冷却结构，这些选择的导热通孔中的每一个在组装操作期间提供从电气部件到热冷却结构的热路径。 热冷却结构适于在组件的操作期间使冷却流体通过。 还提供了制造基板的方法。
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9.发明授权Circuitized substrate with shielded signal lines and plated-thru-holes and method of making same, and electrical assembly and information handling system utilizing same 失效具有屏蔽信号线和电镀通孔的电路基板及其制造方法，以及利用其组合和信息处理系统公开(公告)号：US07679005B2
公开(公告)日：2010-03-16
申请号：US11401401
申请日：2006-04-11
CPC分类号： G06K7/084 , G06K17/00 , G06K19/005 , G06K19/07354 , G06K2017/0064 , H05K1/0221 , H05K1/0222 , H05K3/429 , H05K3/4602 , H05K2201/09809 , H05K2203/0733 , Y10T29/49165
摘要： A circuitized substrate in which selected ones of the signal conductors are substantially surrounded by shielding members which shield the conductors during passage of high frequency signals, e.g., to reduce noise. The shielding members may form solid members which lie parallel and/or perpendicular to the signal conductors, and may also be substantially cylindrical in shape to surround a conductive thru-hole which also forms part of the substrate. An electrical assembly and an information handling system are also defined.
摘要翻译： 电路化基板，其中所选择的信号导体基本上由在高频信号通过期间屏蔽导体的屏蔽构件包围，例如降低噪声。 屏蔽构件可以形成平行和/或垂直于信号导体的固体构件，并且也可以基本上为圆柱形，以包围也形成衬底的一部分的导电通孔。 还定义了电组件和信息处理系统。
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公开(公告)号：US06495772B2
公开(公告)日：2002-12-17
申请号：US09834280
申请日：2001-04-12
申请人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
发明人： Donald O. Anstrom , Bruce J. Chamberlin , John M. Lauffer , Voya R. Markovich , David L. Thomas
IPC分类号： H05K102
CPC分类号： H01L23/5383 , H01L2924/0002 , H01L2924/3011 , H05K1/0263 , H05K1/0265 , H05K3/4602 , H05K3/4611 , H05K2201/0352 , H05K2201/09536 , H05K2201/096 , H05K2203/061 , H05K2203/1581 , H01L2924/00
摘要： A method and structure for implementing dense wiring, in printed circuit board or chip carrier applications, which provides superior electrical characteristics while preserving the system resistance and characteristic impedance requirements. The dense wiring is characterized by requiring that all wires have a sufficient cross-sectional area to ensure the longest wires used do not exceed a maximum resistance by either sorting wire lengths and allowing acceptably “short” wires to use denser circuit lines or by providing short lengths of short circuit lines in those areas where necessary and switching to less dense, lower resistance lines where possible. The disclosure also provides for dense wiring in component areas that can then be converted to low resistance wiring with application of a buried via.
摘要翻译： 一种在印刷电路板或芯片载体应用中实现密集布线的方法和结构，其提供优异的电特性，同时保持系统电阻和特征阻抗要求。 密集布线的特征在于要求所有导线具有足够的横截面积，以确保所使用的最长的导线不会通过分选导线长度而不超过最大电阻，并允许可接受的“短”导线使用更密集的电路线或提供短路 必要时的短路线路长度，尽可能切换到较不密集，较低电阻的线路。 本公开还提供了组件区域中的密集布线，然后可以通过应用埋入通孔将其转换成低电阻布线。
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