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公开(公告)号：US4984048A
公开(公告)日：1991-01-08
申请号：US216536
申请日：1988-07-08
申请人： Kazuhiko Sagara , Tokuo Kure , Eiichi Murakami , Tohru Nakamura , Masanobu Miyao , Masao Kondo , Akitoshi Ishizaka , Yoichi Tamaki
发明人： Kazuhiko Sagara , Tokuo Kure , Eiichi Murakami , Tohru Nakamura , Masanobu Miyao , Masao Kondo , Akitoshi Ishizaka , Yoichi Tamaki
IPC分类号： H01L21/74 , H01L21/763 , H01L29/06 , H01L29/417 , H01L29/732 , H01L29/737
CPC分类号： H01L29/0649 , H01L21/743 , H01L21/763 , H01L29/41716 , H01L29/7325 , H01L29/7327 , H01L29/7378
摘要： Polycrystalline silicon which is provided within a trench for isolating a plurality of bipolar transistors from each other is electrically connected to the collector of one of the bipolar transistor. Since the trench for isolation can also be used to lead out the collector electrode, the required area is minimized. Thus, the arrangement is effective in creasing the integration density.
摘要翻译： 设置在用于将多个双极晶体管彼此隔离的沟槽内的多晶硅电连接到双极晶体管之一的集电极。 由于用于隔离的沟槽也可以用于引出集电极，因此所需的面积被最小化。 因此，这种布置在增加集成密度方面是有效的。
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公开(公告)号：US4984038A
公开(公告)日：1991-01-08
申请号：US194980
申请日：1988-05-17
申请人： Hideo Sunami , Makoto Ohkura , Masanobu Miyao , Kikuo Kusukawa , Masahiro Moniwa , ShinIchiro Kimura , Terunori Warabisako , Tokuo Kure
发明人： Hideo Sunami , Makoto Ohkura , Masanobu Miyao , Kikuo Kusukawa , Masahiro Moniwa , ShinIchiro Kimura , Terunori Warabisako , Tokuo Kure
IPC分类号： H01L21/762 , H01L27/108
CPC分类号： H01L21/762 , H01L27/10841
摘要： The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
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公开(公告)号：US5237528A
公开(公告)日：1993-08-17
申请号：US822325
申请日：1992-01-17
申请人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
发明人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
IPC分类号： G11C11/404 , H01L27/108 , H01L29/94
CPC分类号： G11C11/404 , H01L27/10829 , H01L27/10841 , H01L29/945
摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。
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公开(公告)号：US5214496A
公开(公告)日：1993-05-25
申请号：US452683
申请日：1989-12-19
申请人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
发明人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
IPC分类号： G11C11/404 , H01L27/108 , H01L29/94
CPC分类号： H01L27/10829 , G11C11/404 , H01L27/10841 , H01L29/945
摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
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公开(公告)号：US4901128A
公开(公告)日：1990-02-13
申请号：US934556
申请日：1986-11-24
申请人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
发明人： Hideo Sunami , Tokuo Kure , Masanobu Miyao , Yoshifumi Kawamoto , Katsuhiro Shimohigashi , Yoshio Sakai , Osamu Minato , Toshiaki Masuhara , Mitsumasa Koyanagi , Shinji Shimizu
IPC分类号： G11C11/404 , H01L27/108 , H01L29/94
CPC分类号： G11C11/404 , H01L27/10829 , H01L27/10841 , H01L29/945
摘要： A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
摘要翻译： 半导体存储器包括具有数据存储部分的电容器和绝缘栅场效应晶体管。 该电容器由在半导体衬底中形成的沟槽的侧壁和底部以及形成在侧壁和基底上的电容器电极在绝缘膜上形成并且电连接 到绝缘栅场效应晶体管的源极或漏极。 提供了各种实施例，用于减小尺寸并防止其它存储单元之间的泄漏，包括形成叠层电容器，在电容器上形成晶体管，使用用于晶体管的绝缘体上硅布置，形成公共电容器板并提供高杂质层 底物。
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公开(公告)号：US4751557A
公开(公告)日：1988-06-14
申请号：US904397
申请日：1986-09-08
申请人： Hideo Sunami , Tokuo Kure , Yoshifumi Kawamoto , Masao Tamura , Masanobu Miyao
发明人： Hideo Sunami , Tokuo Kure , Yoshifumi Kawamoto , Masao Tamura , Masanobu Miyao
IPC分类号： G11C11/401 , H01L21/033 , H01L21/763 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/78 , G11C11/40
CPC分类号： H01L21/763 , H01L21/033 , H01L27/10841
摘要： A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
摘要翻译： 一种半导体存储器，其中每个电容器的一部分形成在由形成在半导体衬底中的凹部包围的岛状区域的侧壁上，并且岛状区域和其它区域通过凹部电隔离。
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公开(公告)号：US4984030A
公开(公告)日：1991-01-08
申请号：US201100
申请日：1988-05-31
申请人： Hideo Sunami , Tokuo Kure , Yoshifumi Kawamoto , Masao Tamura , Masanobu Miyao
发明人： Hideo Sunami , Tokuo Kure , Yoshifumi Kawamoto , Masao Tamura , Masanobu Miyao
IPC分类号： G11C11/401 , H01L21/033 , H01L21/763 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L21/763 , H01L21/033 , H01L27/10841
摘要： A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
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公开(公告)号：US4937641A
公开(公告)日：1990-06-26
申请号：US81142
申请日：1987-08-03
申请人： Hideo Sunami , Makoto Ohkura , Masanobu Miyao , Kikuo Kusukawa , Masahiro Moniwa , ShinIchiro Kimura , Terunori Warabisako , Tokuo Kure
发明人： Hideo Sunami , Makoto Ohkura , Masanobu Miyao , Kikuo Kusukawa , Masahiro Moniwa , ShinIchiro Kimura , Terunori Warabisako , Tokuo Kure
IPC分类号： H01L21/762 , H01L27/108
CPC分类号： H01L21/762 , H01L27/10841
摘要： The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
摘要翻译： 作为电容器的电极面的主要部分，使用在Si衬底中挖出的凹部的侧壁部分，由此电极面积扩大而不扩大平面面积。 因此，可以获得期望的电容器电容，而不会增加绝缘膜的破坏，这归因于传统的绝缘膜变薄的方法。 此外，在Si衬底上形成垂直开关晶体管，由此可以将Si衬底完全用于电容器的形成。
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公开(公告)号：US5357131A
公开(公告)日：1994-10-18
申请号：US93033
申请日：1993-07-19
申请人： Hideo Sunami , Tokuo Kure , Yoshifumi Kawamoto , Masao Tamura , Masanobu Miyao
发明人： Hideo Sunami , Tokuo Kure , Yoshifumi Kawamoto , Masao Tamura , Masanobu Miyao
IPC分类号： H01L21/033 , H01L21/308 , H01L27/108 , H01L27/12
CPC分类号： H01L27/1203 , H01L21/0337 , H01L21/3086 , H01L27/1082 , H01L27/10832 , H01L27/10841
摘要： A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
摘要翻译： 一种半导体存储器，其中每个电容器的一部分形成在由形成在半导体衬底中的凹部包围的岛状区域的侧壁上，并且岛状区域和其它区域通过凹部电隔离。
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公开(公告)号：US5241197A
公开(公告)日：1993-08-31
申请号：US759772
申请日：1991-09-13
IPC分类号： H01L27/085 , H01L29/165 , H01L29/737 , H01L29/778 , H01L29/80
CPC分类号： H01L29/7378 , H01L27/085 , H01L29/165 , H01L29/7373 , H01L29/7782 , H01L29/802
摘要： A transistor having a high carrier mobility and suited for a high-speed operation can be formed by utilizing a fact that the carrier mobility in a strained germanium layer is large. A strain control layer is provided beneath the germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer in a predetermined range is used to generate the compressive strain surely.
摘要翻译： 可以通过利用应变锗层中的载流子迁移率大的事实来形成具有高载流子迁移率且适于高速操作的晶体管。 在锗层下方设置应变控制层，以在锗层上施加压缩应变，并且使用预定范围内的应变控制层的组成以确定地产生压缩应变。
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