公开(公告)号：US5661078A

公开(公告)日：1997-08-26

申请号：US449674

申请日：1995-05-24

申请人： Kazuyuki Yahiro ,  Shuji Itonaga

发明人： Kazuyuki Yahiro ,  Shuji Itonaga

IPC分类号： H01L21/3205 ,  H01L21/268 ,  H01L21/288 ,  H01L21/302 ,  H01L21/768 ,  H01L23/52 ,  H01L21/283

CPC分类号： H01L21/288

摘要： In a semiconductor device according to the present invention, a diffusion layer is formed on a silicon substrate, and a Silicon oxide film is deposited thereon. A hole communicating with the diffusion layer is formed in the silicon oxide film. A silver bromide emulsion is applied to the silicon oxide film having the hole by the spin coat technique. The silver bromide emulsion is irradiated with light through a mask to leave only that portion of the emulsion which is exposed by the light. By doing so, a metal wiring is formed integrally with a via hole, and thus decreased in resistance and suitable for forming the via hole. Consequently, a semiconductor device having such a wiring can be obtained easily, inexpensively.

摘要翻译： 在根据本发明的半导体器件中，在硅衬底上形成扩散层，并在其上淀积氧化硅膜。 在氧化硅膜中形成与扩散层连通的孔。 通过旋涂法将溴化银乳剂施加到具有孔的氧化硅膜上。 溴化银乳剂通过掩模用光照射，仅留下被光暴露的那部分乳液。 通过这样做，金属布线与通孔形成一体，因此电阻降低并且适于形成通孔。 因此，可以容易地，廉价地获得具有这种布线的半导体器件。

公开(公告)号：US20100181546A1

公开(公告)日：2010-07-22

申请号：US12545326

申请日：2009-08-21

申请人： Kazuhiko Yamamoto ,  Kazuyuki Yahiro ,  Tsukasa Nakai

发明人： Kazuhiko Yamamoto ,  Kazuyuki Yahiro ,  Tsukasa Nakai

IPC分类号： H01L47/00 ,  H01L21/16

CPC分类号： H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675

摘要： A nonvolatile semiconductor memory using carbon related films as variable resistance films includes bottom electrodes formed above a substrate, buffer layers formed on the bottom electrodes and each formed of a film containing nitrogen and containing carbon as a main component, variable resistance films formed on the buffer layers and each formed of a film containing carbon as a main component and the electrical resistivity thereof being changed according to application of voltage or supply of current, and top electrodes formed on the variable resistance films.

摘要翻译： 使用碳相关膜作为可变电阻膜的非易失性半导体存储器包括形成在衬底上的底部电极，形成在底部电极上的缓冲层，并且每个由含有氮并含有碳作为主要成分的膜形成，形成在缓冲器上的可变电阻膜 层，并且各自由含有碳作为主要成分的膜形成，并且其电阻率根据施加电压或电流供应而变化，以及形成在可变电阻膜上的顶部电极。

公开(公告)号：US20050145500A1

公开(公告)日：2005-07-07

申请号：US10998970

申请日：2004-11-30

申请人： Hiroshi Toyoda ,  Yoshitaka Matsui ,  Kazuyuki Yahiro ,  Junsei Yamabe ,  Shiro Mishima ,  Takahito Nagamatsu

发明人： Hiroshi Toyoda ,  Yoshitaka Matsui ,  Kazuyuki Yahiro ,  Junsei Yamabe ,  Shiro Mishima ,  Takahito Nagamatsu

IPC分类号： C25D5/02 ,  C25D5/18 ,  C25D7/12 ,  C25D17/00 ,  C25D17/10 ,  C25D21/00 ,  H01L21/00 ,  H01L21/288 ,  H01L21/768

CPC分类号： C25D7/123 ,  C25D17/001 ,  C25D17/002 ,  C25D17/10 ,  C25D21/00 ,  H01L21/2885 ,  H01L21/76877

摘要： According to an embodiment of the present invention, a plating apparatus, including: a plating solution tank configured to store a plating solution; a holder configured to hold a substrate on which a seed layer is formed in said plating solution tank; a first anode disposed in said plating solution tank, composed of a more anodic material in its oxidation-reduction potential than the oxidation-reduction potential of a metal composing the seed layer, and electrically connectable to the seed layer of the substrate held by said holder; and a second anode disposed in said plating solution tank, capable of applying a voltage between the seed layer of the substrate held by holder, is provided.

摘要翻译： 根据本发明的一个实施例，一种电镀设备，包括：电镀溶液槽，被配置为存储电镀溶液; 保持器，其构造成在所述电镀液槽中保持形成有种子层的基板; 设置在所述电镀液槽中的第一阳极，由比其构成种子层的金属的氧化还原电位的氧化还原电位更多的阳极材料构成，并且可电连接到由所述保持体保持的衬底的籽晶层 ; 以及设置在所述电镀液槽中的第二阳极，能够在由保持器保持的基板的籽晶层之间施加电压。

公开(公告)号：US07803706B2

公开(公告)日：2010-09-28

申请号：US12408593

申请日：2009-03-20

申请人： Toshiaki Idaka ,  Kazuyuki Yahiro

发明人： Toshiaki Idaka ,  Kazuyuki Yahiro

IPC分类号： H01L21/4763 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/3105 ,  H01L29/7843

摘要： Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.

摘要翻译： 公开了一种半导体器件制造方法，其中形成氮化硅膜以覆盖形成在半导体衬底上的n沟道晶体管并且在沟道长度方向上施加拉应力到n沟道晶体管的沟道，该方法 包括：在n沟道晶体管上形成第一层氮化硅膜; 用紫外线照射第一层氮化硅膜; 并且在紫外线照射之后，形成比第一层氮化硅膜上方的第一层氮化硅膜薄的至少一个氮化硅膜。 通过各个步骤形成施加拉伸应力的氮化硅膜。

公开(公告)号：US5683940A

公开(公告)日：1997-11-04

申请号：US575851

申请日：1995-12-20

申请人： Kazuyuki Yahiro

发明人： Kazuyuki Yahiro

IPC分类号： C30B25/16 ,  C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L27/00

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  Y10S438/902

摘要： In a method of manufacturing a semiconductor device, a first plasma insulating film having a thickness of 0.1 .mu.m or more is formed on the semiconductor substrate with lower-surface wirings thereon. The semiconductor substrate is moved into a pressure-reduced CVD device, and then an SiH.sub.4 gas and H.sub.2 O.sub.2 are supplied into the pressure-reduced CVD device to react them to each other in a vacuum of 650 Pa or less within the temperature range of -10.degree. C. to +10.degree. C. to form a reflow SiO.sub.2 film having a thickness of 0.4 .mu.m to 1.4 .mu.m on the semiconductor substrate. The semiconductor substrate is put in a vacuum of 6.5 pascal for 30 seconds or more. Thereafter, the semiconductor substrate is put at a high temperature of 300.degree. C. to 450.degree. C. for 120 to 600 seconds. A second plasma insulating film having a thickness of 0.3 .mu.m or more and serving as a cap film is formed on the semiconductor substrate. The crack resistance of the reflow insulating film formed in the above steps is improved, and the flatness of the reflow insulating film is improved.

摘要翻译： 在制造半导体器件的方法中，在其上具有较低表面布线的半导体衬底上形成厚度为0.1μm或更大的第一等离子体绝缘膜。 将半导体衬底移动到减压CVD器件中，然后将SiH 4气体和H 2 O 2供给到减压CVD器件中，以在-10Pa以下的温度范围内在650Pa以下的真空中彼此反应 ℃至+10℃，以在半导体衬底上形成厚度为0.4μm至1.4μm的回流SiO 2膜。 将半导体衬底置于6.5帕斯卡的真空中30秒以上。 此后，将半导体衬底置于300℃至450℃的高温下120至600秒。 在半导体衬底上形成厚度为0.3μm以上且用作盖膜的第二等离子体绝缘膜。 在上述步骤中形成的回流绝缘膜的抗裂性得到改善，并且提高了回流绝缘膜的平坦度。

公开(公告)号：US20050145482A1

公开(公告)日：2005-07-07

申请号：US10973350

申请日：2004-10-27

申请人： Hidenao Suzuki ,  Koji Mishima ,  Hiroyuki Kanda ,  Kazufumi Nomura ,  Kunihito Ide ,  Kazuyuki Yahiro ,  Hiroshi Toyoda ,  Tetsuo Matsuda

发明人： Hidenao Suzuki ,  Koji Mishima ,  Hiroyuki Kanda ,  Kazufumi Nomura ,  Kunihito Ide ,  Kazuyuki Yahiro ,  Hiroshi Toyoda ,  Tetsuo Matsuda

IPC分类号： C25D7/12 ,  C25D17/00 ,  C25D17/06 ,  C25D21/10 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/68 ,  H01L21/683

CPC分类号： H01L21/2885 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06

摘要： An apparatus and a method for processing substrate are generally used for apparatuses for wet-type process of substrate, such as an electrolytic processing apparatus for use in forming interconnects by embedding a metal such as copper (Cu) or the like in fine interconnect patterns (recesses) that are formed in a substrate such as a semiconductor wafer and for use in forming bumps for electrical connections. The substrate processing apparatus includes: a substrate holder for holding a substrate; a first electrode for contacting the substrate to supply electricity to a processing surface of the substrate; a second electrode disposed so as to face the processing surface of the substrate held by the substrate holder; and a processing liquid supply section for supplying a processing liquid into the space between the processing surface of the substrate held by the substrate holder and the second electrode, wherein the substrate holder is designed to rotate the substrate during processing in such a manner that acceleration and slowdown and/or normal rotation and reverse rotation are repeated.

摘要翻译： 用于处理衬底的装置和方法通常用于衬底的湿式处理装置，例如通过将金属（例如铜）（Cu）等嵌入到精细互连图案中而形成互连件的电解处理装置 凹部），其形成在诸如半导体晶片的基板中，并且用于形成用于电连接的凸块。 基板处理装置包括：用于保持基板的基板保持件; 第一电极，用于接触所述衬底以向所述衬底的处理表面供电; 第二电极，其设置成面对由所述基板保持器保持的所述基板的处理表面; 以及处理液体供应部分，用于将处理液体供应到由基板保持器保持的基板的处理表面与第二电极之间的空间中，其中基板保持器设计成在加工期间使基板旋转， 重复减速和/或正常旋转和反向旋转。

公开(公告)号：US6153542A

公开(公告)日：2000-11-28

申请号：US862249

申请日：1997-05-23

申请人： Kazuyuki Yahiro

发明人： Kazuyuki Yahiro

IPC分类号： C30B25/16 ,  C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L27/00 ,  H01L21/44

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  Y10S438/902

摘要： In a method of manufacturing a semiconductor device, a first plasma insulating film having a thickness of 0.1 .mu.m or more is formed on the semiconductor substrate with lower-surface wirings thereon. The semiconductor substrate is moved into a pressure-reduced CVD device, and then an SiH.sub.4 gas and H.sub.2 O.sub.2 are supplied into the pressure-reduced CVD device to react them to each other in a vacuum of 650 Pa or less within the temperature range of -10.degree. C. to +10.degree. C. to form a reflow SiO.sub.2 film having a thickness of 0.4 .mu.m to 1.4 .mu.m on the semiconductor substrate. The semiconductor substrate is put in a vacuum of 6.5 pascal for 30 seconds or more. Thereafter, the semiconductor substrate is put at a high temperature of 300.degree. C. to 450.degree. C. for 120 to 600 seconds. A second plasma insulating film having a thickness of 0.3 .mu.m or more and serving as a cap film is formed on the semiconductor substrate. The crack resistance of the reflow insulating film formed in the above steps is improved, and the flatness of the reflow insulating film is improved.

摘要翻译： 在制造半导体器件的方法中，在其上具有较低表面布线的半导体衬底上形成厚度为0.1μm或更大的第一等离子体绝缘膜。 将半导体衬底移动到减压CVD器件中，然后将SiH 4气体和H 2 O 2供给到减压CVD器件中，以在-10Pa以下的温度范围内在650Pa以下的真空中彼此反应 ℃至+10℃，以在半导体衬底上形成厚度为0.4μm至1.4μm的回流SiO 2膜。 将半导体衬底置于6.5帕斯卡的真空中30秒以上。 此后，将半导体衬底置于300℃至450℃的高温下120至600秒。 在半导体衬底上形成厚度为0.3μm以上且用作盖膜的第二等离子体绝缘膜。 在上述步骤中形成的回流绝缘膜的抗裂性得到改善，并且提高了回流绝缘膜的平坦度。

公开(公告)号：US08334525B2

公开(公告)日：2012-12-18

申请号：US12825975

申请日：2010-06-29

申请人： Tsukasa Nakai ,  Hiroyuki Fukumizu ,  Yasuhiro Nojiri ,  Motoya Kishida ,  Kazuyuki Yahiro ,  Yasuhiro Satoh

发明人： Tsukasa Nakai ,  Hiroyuki Fukumizu ,  Yasuhiro Nojiri ,  Motoya Kishida ,  Kazuyuki Yahiro ,  Yasuhiro Satoh

IPC分类号： H01L29/02

CPC分类号： H01L45/04 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/1616 ,  H01L45/1625

摘要： According to one embodiment, a variable resistance layer includes a mixture of a first compound and a second compound. The first compound includes carbon (C) as well as at least one element selected from a group of elements G1. The group of elements G1 consists of hydrogen (H), boron (B), nitrogen (N), silicon (Si), and titanium (Ti). The second compound includes at least one compound selected from a group of compounds G2. The group of compounds G2 consists of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), carbon nitride (C3N4), boron nitride (BN), aluminum nitride (AlN), aluminum oxide (Al2O3), and silicon carbide (SiC). Concentration of the first compound in the variable resistance layer is not less than 30 volume percent, and not more than 70 volume percent.

摘要翻译： 根据一个实施方案，可变电阻层包括第一化合物和第二化合物的混合物。 第一化合物包括碳（C）以及选自元素组G1的至少一种元素。 元素组G1由氢（H），硼（B），氮（N），硅（Si）和钛（Ti）组成。 第二化合物包括选自化合物G2的至少一种化合物。 化合物组G2由氧化硅（SiO 2），氮氧化硅（SiON），氮化硅（Si 3 N 4），碳氮化物（C 3 N 4），氮化硼（BN），氮化铝（AlN），氧化铝（Al 2 O 3）和 碳化硅（SiC）。 可变电阻层中第一化合物的浓度不小于30体积％，不大于70体积％。

公开(公告)号：US07960764B2

公开(公告)日：2011-06-14

申请号：US12805940

申请日：2010-08-25

申请人： Toshiaki Idaka ,  Kazuyuki Yahiro

发明人： Toshiaki Idaka ,  Kazuyuki Yahiro

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L23/58

CPC分类号： H01L21/3105 ,  H01L29/7843

摘要： Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.

摘要翻译： 公开了一种半导体器件制造方法，其中形成氮化硅膜以覆盖形成在半导体衬底上的n沟道晶体管并且在沟道长度方向上施加拉应力到n沟道晶体管的沟道，该方法 包括：在n沟道晶体管上形成第一层氮化硅膜; 用紫外线照射第一层氮化硅膜; 并且在紫外线照射之后，形成比第一层氮化硅膜上方的第一层氮化硅膜薄的至少一个氮化硅膜。 通过各个步骤形成施加拉伸应力的氮化硅膜。

公开(公告)号：US20090283874A1

公开(公告)日：2009-11-19

申请号：US12408593

申请日：2009-03-20

申请人： Toshiaki IDAKA ,  Kazuyuki Yahiro

发明人： Toshiaki IDAKA ,  Kazuyuki Yahiro

IPC分类号： H01L23/58 ,  H01L21/469

CPC分类号： H01L21/3105 ,  H01L29/7843

摘要： Disclosed is a semiconductor device manufacturing method in which a silicon nitride film is formed to cover an n-channel transistor formed on a semiconductor substrate and to apply a tensile stress in a channel length direction to a channel of the n-channel transistor, the method includes: forming a first-layer silicon nitride film above the n-channel transistor; irradiating the first-layer silicon nitride film with ultraviolet radiation; and after the ultraviolet irradiation, forming at least one silicon nitride film thinner than the first-layer silicon nitride film above the first-layer silicon nitride film. Silicon nitride films formed to apply the tensile stress is formed by respective steps.

摘要翻译： 公开了一种半导体器件制造方法，其中形成氮化硅膜以覆盖形成在半导体衬底上的n沟道晶体管并且在沟道长度方向上施加拉应力到n沟道晶体管的沟道，该方法 包括：在n沟道晶体管上形成第一层氮化硅膜; 用紫外线照射第一层氮化硅膜; 并且在紫外线照射之后，形成比第一层氮化硅膜上方的第一层氮化硅膜薄的至少一个氮化硅膜。 通过各个步骤形成施加拉伸应力的氮化硅膜。