Electrical performance enhanced wafer level chip scale package with ground
    5.
    发明授权
    Electrical performance enhanced wafer level chip scale package with ground 有权
    电性能增强晶圆级芯片级封装带地

    公开(公告)号:US06656827B1

    公开(公告)日:2003-12-02

    申请号:US10272629

    申请日:2002-10-17

    IPC分类号: H01L2144

    摘要: A method including providing a first substrate having a first bond pad and a second bond pad; forming a subassembly comprising securing a second substrate to the first substrate with a ground layer interposed between the first substrate and the second substrate; forming a first trench in the subassembly through the first substrate so that the trench is defined at least in part by a side wall of the first substrate and through at least a portion of the ground layer; and forming a first electrically conductive layer overlying the first bond pad, the side wall of the first substrate and overlying a portion of the ground layer.

    摘要翻译: 一种包括提供具有第一接合焊盘和第二接合焊盘的第一基板的方法; 形成子组件,其包括将第二衬底固定到所述第一衬底上,所述接地层置于所述第一衬底和所述第二衬底之间; 通过所述第一衬底在所述子组件中形成第一沟槽,使得所述沟槽至少部分地由所述第一衬底的侧壁和所述接地层的至少一部分限定; 以及形成覆盖所述第一接合焊盘,所述第一基板的侧壁并覆盖所述接地层的一部分的第一导电层。