公开(公告)号：US5215677A

公开(公告)日：1993-06-01

申请号：US317080

申请日：1989-02-28

申请人： Kenichi Narita ,  Shoji Nakanishi

发明人： Kenichi Narita ,  Shoji Nakanishi

IPC分类号： C09K19/30 ,  G02F1/1337

CPC分类号： C09K19/3001 ,  G02F1/133711

摘要： A chiral nematic type liquid crystal display device in which the twist angle of a torsional structure of a liquid crystal layer is as large as 180.degree. to 360.degree. and the birefringence of liquid crystal molecules is utilized. This liquid crystal display device is characterized in that: a liquid crystal layer is disposed between opposed substrates and orientation films formed of straight chain polymer having fluoro-alkyl side chain C.sub.n H.sub.m F.sub.2n+1-m (n being a natural number and m being a natural number of 0 or 2n or less) are provided on the respective inner surfaces of said substrates facing the liquid crystal layer.

摘要翻译： 一种手性向列型液晶显示装置，其中液晶层的扭转结构的扭曲角大于180度至360度，并且利用了液晶分子的双折射。 该液晶显示装置的特征在于：液晶层设置在相对的基板和由具有氟烷基侧链CnHmF2n + 1-m（n为自然数，m为自然数）的直链聚合物形成的取向膜 0或2n以下）设置在面向液晶层的所述基板的各个内表面上。

公开(公告)号：US5274485A

公开(公告)日：1993-12-28

申请号：US891849

申请日：1992-06-01

申请人： Kenichi Narita ,  Takao Yamauchi ,  Shoji Nakanishi ,  Hiroshi Inamura ,  Makoto Murakami

发明人： Kenichi Narita ,  Takao Yamauchi ,  Shoji Nakanishi ,  Hiroshi Inamura ,  Makoto Murakami

IPC分类号： G02F1/1365 ,  H01L45/00 ,  G02F1/1343 ,  H01L27/02 ,  H01L29/46 ,  H01L29/88

CPC分类号： H01L45/00 ,  G02F1/1365

摘要： A liquid crystal display includes an insulating substrate, a first metal layer formed on the substrate, a first insulating layer including an oxide of tantalum nitride with high ratio of nitrization formed on the first metal layer, a second insulating layer including an oxide of tantalum nitride with low ratio of nitrization formed on the first insulating layer, and a second metal layer formed on the second insulating layer.

摘要翻译： 液晶显示器包括绝缘基板，形成在基板上的第一金属层，在第一金属层上形成的氮化氮比率高的氮化钽的氧化物的第一绝缘层，包含氮化钽的氧化物的第二绝缘层 在第一绝缘层上形成的氮化比率低，以及形成在第二绝缘层上的第二金属层。

公开(公告)号：US09299629B2

公开(公告)日：2016-03-29

申请号：US12932560

申请日：2011-02-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L21/78 ,  H01L23/29 ,  H01L23/00 ,  H01L23/58

CPC分类号： H01L23/293 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate provided with a scribe region and an IC region. A first insulating film is disposed on the semiconductor substrate across the scribe region and the IC region. At least one separation groove is provided in the first insulating film in the scribe region. Side walls made of a plug metal film are formed only on respective lateral walls of the separation groove so that the plug metal film on the lateral walls does not extend out of the separation groove and does not exist on an upper surface of the first insulating film. A second insulating film covers at least the side walls formed on the respective lateral walls of the separation groove so that the side walls are disposed under the second insulating film.

摘要翻译： 半导体器件具有设置有划线区域和IC区域的半导体衬底。 第一绝缘膜设置在跨越划线区域和IC区域的半导体衬底上。 在划线区域的第一绝缘膜中设置至少一个分隔槽。 由插塞金属膜制成的侧壁仅形成在分隔槽的相应侧壁上，使得侧壁上的插塞金属膜不会从分离槽延伸出来，并且不存在于第一绝缘膜的上表面上 。 第二绝缘膜至少覆盖形成在分隔槽的各个侧壁上的侧壁，使得侧壁设置在第二绝缘膜下方。

公开(公告)号：US20050221553A1

公开(公告)日：2005-10-06

申请号：US11092794

申请日：2005-03-29

申请人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

发明人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  H01L29/7883

摘要： In a non-volatile memory in which a floating gate is provided above a single crystal control region, a potential of wiring, which is arranged above the floating gate, has a capacitive coupling with respect to the floating gate, or even one part in and on an insulating film on the floating gate is included or attached with electric charge, thereby varying the gate threshold voltage of the floating gate non-volatile memory measured from the single crystal control region. In order to solve the above-described problems, the present invention provides following methods. A shield conductive film is provided above a floating gate through a shield insulating film. For the shield insulating film, there is used an insulating film formed by not a deposition method in which a gas atmosphere containing un-balanced charge particles such as excess electrons or excess ions contacts with a wafer surface, such as plasma CVD but a deposition method in which neutral molecules/atoms come flying immediately above the wafer, for example, thermal CVD, radical CVD, photo-assisted CVD, or thermal oxidization.

摘要翻译： 在浮动栅极设置在单晶体控制区域之上的非易失性存储器中，布置在浮置栅极上方的布线电位具有相对于浮动栅极的电容耦合，或甚至一个部分 在浮栅上的绝缘膜上包含或附加电荷，从而改变从单晶控制区测量的浮栅非易失性存储器的栅极阈值电压。 为了解决上述问题，本发明提供以下方法。 屏蔽导电膜通过屏蔽绝缘膜设置在浮栅上。 对于屏蔽绝缘膜，使用通过不是沉积方法形成的绝缘膜，其中包含诸如过电子或过量离子的非平衡电荷颗粒的气体气氛与晶片表面接触，诸如等离子体CVD，但是沉积方法 其中中性分子/原子直接在晶片上方飞行，例如热CVD，自由基CVD，光辅助CVD或热氧化。

公开(公告)号：US20060231020A1

公开(公告)日：2006-10-19

申请号：US10548289

申请日：2004-03-01

申请人： Yoshihide Ishibashi ,  Powei Sung ,  Shinya Ohmura ,  Chikako Azuma ,  Honggi Bae ,  Hiroshi Sasaki ,  Shoji Nakanishi

发明人： Yoshihide Ishibashi ,  Powei Sung ,  Shinya Ohmura ,  Chikako Azuma ,  Honggi Bae ,  Hiroshi Sasaki ,  Shoji Nakanishi

IPC分类号： B05C5/00 ,  B05C1/08

CPC分类号： B41F3/20

摘要： Printing unevenness caused in forming a polarizing film by printing an ink liquid having a dichromatic dye is minimized to provide satisfactory LCD display characteristics. Bearings are erected on opposite sides of a table and are formed with vertical slots, into which the opposite ends of an axle of a printing cylinder are dropped, whereby the axle of the printing cylinder is loosely fitted in the right and left bearings. The bearings are horizontally movably constructed and connected to a horizontal motion drive (not shown). Further, right and left weights of equal heaviness are attached to the opposite sides of the axle of the printing cylinder. In producing a polarizing film, a substrate is placed on the table and a format having a number of fine grooves is attached to the printing cylinder and placed on the substrate. Ink liquid having a dichromatic dye is applied to the format to form a thin film of ink liquid on the format surface, and the bearings are horizontally moved along the printing direction. Thereby, the printing cylinder rolls on the substrate, so that the thin film of ink liquid is transferred from the format to the substrate.

摘要翻译： 通过印刷具有二色染料的油墨形成偏振膜而引起的印刷不均匀性被最小化以提供令人满意的LCD显示特性。 轴承架竖立在桌子的两侧，并形成有垂直槽，印刷滚筒的轴的相对端部分落入其中，从而使印刷滚筒的轴松动地安装在左右轴承中。 轴承水平移动构造并连接到水平运动驱动器（未示出）。 此外，相同重量的左右重物附着在印版滚筒的轴的相对两侧。 在制造偏光膜时，将基板放置在工作台上，并且将具有多个细槽的格式附着到印刷滚筒并放置在基板上。 将具有二色染料的油墨以格式施加，以在格式表面上形成墨液薄膜，并且轴承沿印刷方向水平移动。 因此，印刷滚筒在基板上滚动，使得墨液的薄膜从格式转移到基板。

公开(公告)号：US07473957B2

公开(公告)日：2009-01-06

申请号：US11092794

申请日：2005-03-29

申请人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

发明人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

IPC分类号： H01L27/108

CPC分类号： H01L29/7885 ,  H01L29/7883

摘要： A floating non-volatile memory has a substrate and source and drain regions disposed in a surface region of the substrate and spaced apart from each other with a channel forming semiconductor region disposed therebetween. A gate insulating film is disposed on the channel forming semiconductor region. A single crystal control region is disposed in the surface region of the substrate and is electrically separated from the channel forming semiconductor region. A control gate insulating film is disposed on the single crystal control region. A floating gate is disposed on the control gate insulating film and is capacitively coupled with the single crystal control region. A chemical-vapor-deposited shield insulating film is formed in a gas atmosphere charge-balanced on the floating gate. A shield conductive film is disposed on the chemical-vapor-deposited shield insulating film and capacitively coupled with the floating gate.

摘要翻译： 浮动非易失性存储器具有衬底和源极和漏极区域，其设置在衬底的表面区域中并且彼此间隔开，并且沟道形成半导体区域位于它们之间。 栅极绝缘膜设置在沟道形成半导体区域上。 单晶控制区域设置在基板的表面区域中，并与沟道形成半导体区域电分离。 控制栅绝缘膜设置在单晶控制区上。 浮置栅极设置在控制栅绝缘膜上并与单晶控制区电容耦合。 在浮动栅极上电荷平衡的气体气氛中形成化学气相沉积的屏蔽绝缘膜。 屏蔽导电膜设置在化学气相沉积的屏蔽绝缘膜上并与浮动栅极电容耦合。

公开(公告)号：US06492692B1

公开(公告)日：2002-12-10

申请号：US09407382

申请日：1999-09-28

申请人： Kazutoshi Ishii ,  Naoto Inoue ,  Koushi Maemura ,  Shoji Nakanishi ,  Yoshikazu Kojima ,  Kiyoaki Kadoi ,  Takao Akiba ,  Yasuhiro Moya ,  Kentaro Kuhara

发明人： Kazutoshi Ishii ,  Naoto Inoue ,  Koushi Maemura ,  Shoji Nakanishi ,  Yoshikazu Kojima ,  Kiyoaki Kadoi ,  Takao Akiba ,  Yasuhiro Moya ,  Kentaro Kuhara

IPC分类号： H01L2972

CPC分类号： H01L24/05 ,  H01L21/78 ,  H01L23/53228 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05017 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06051 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/75252 ,  H01L2224/85201 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.

摘要翻译： 为了减小芯片的面积，提高制造效率，降低诸如具有多个输出焊盘的驱动器集成电路等半导体装置以及诸如电子时钟之类的电子电路装置的成本。 在驱动晶体管或连接到其的逻辑电路上分别布置有两个重叠的输出焊盘。 此外，不仅铝互连而且凸起电极或阻挡金属用于半导体器件的互连。 在半导体集成电路以面朝下的方式电粘接到印刷电路板的情况下，设置在半导体集成电路上的焊料凸块和印刷电路板的互连直接连接，从而实现 电气连接。 在这种情况下，作为半导体集成电路的外部连接端子的突起电极层叠在晶体管上。

公开(公告)号：US5145797A

公开(公告)日：1992-09-08

申请号：US648516

申请日：1991-01-30

申请人： Shoji Nakanishi

发明人： Shoji Nakanishi

IPC分类号： H01L21/8247 ,  H01L21/266 ,  H01L21/336 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/266 ,  H01L29/6659

摘要： In a MOS transistor or memory cell that uses a thin oxide film as a gate insulation film, ion-implantation-induced damage protection films (mask oxide films) are formed on side walls of a polysilicon gate electrode to minimize flaws in the structure of the thin oxide film right under the polysilicon gate electrode edge, which are induced by the ion implantation performed during the process of forming self-aligned source and drain regions.

摘要翻译： 在使用薄氧化膜作为栅极绝缘膜的MOS晶体管或存储单元中，在多晶硅栅电极的侧壁上形成离子注入诱导的损伤保护膜（掩模氧化物膜），以最小化结构中的缺陷 在多晶硅栅极电极边缘正下方的薄氧化膜，它们是在形成自对准的源极和漏极区域的过程中进行的离子注入引起的。

公开(公告)号：US08324687B2

公开(公告)日：2012-12-04

申请号：US12695443

申请日：2010-01-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L23/62

CPC分类号： H01L23/62 ,  H01L27/0259 ,  H01L27/027 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/423 ,  H01L29/735 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device comprising: a PW layer formed at a surface of a semiconductor substrate; an NW layer formed at the surface of the semiconductor substrate to be in contact with the PW layer; a p+ base layer formed at the surface of the semiconductor substrate in the PW layer; an n+ collector layer formed at the surface of the semiconductor substrate in the NW layer; an n+ emitter layer located between the p+ base layer and the n+ collector layer and formed at the surface of the semiconductor substrate in the PW layer; and an n± layer formed between the n+ collector layer and the PW layer to be in contact with the n+ collector layer.

摘要翻译： 提供一种半导体器件，包括：在半导体衬底的表面上形成的PW层; 形成在所述半导体衬底的与所述PW层接触的表面的NW层; 形成在PW层中的半导体衬底的表面的p +基层; 形成在所述NW层的半导体衬底的表面的n +集电体层; 位于p +基极层和n +集电极层之间并形成在PW层中的半导体衬底的表面的n +发射极层; 以及形成在n +集电极层和PW层之间的与n +集电极层接触的n +层。

公开(公告)号：US20110221043A1

公开(公告)日：2011-09-15

申请号：US12932560

申请日：2011-02-28

申请人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

发明人： Tomomitsu Risaki ,  Shoji Nakanishi ,  Koichi Shimazaki

IPC分类号： H01L23/544 ,  H01L21/28

CPC分类号： H01L23/293 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device suitable for preventing film peeling due to dicing and preventing abnormal discharge. The semiconductor device includes a scribe region (003) and an IC region (004). At least one separation groove (007) is provide in an inter-layer insulating film (002) in the scribe region 003, and a side wall (011) made of a plug metal film is formed on each lateral wall of the separation groove (007). A passivation film is provided to cover at least the side walls (011).

摘要翻译： 提供一种半导体装置，其适用于防止由于切割而导致的膜剥离并防止异常放电。 半导体器件包括划线区（003）和IC区（004）。 在划线区域003中的层间绝缘膜（002）中设置至少一个分离槽（007），并且在分隔槽的每个侧壁上形成由插塞金属膜制成的侧壁（011） 007）。 提供钝化膜以至少覆盖侧壁（011）。