公开(公告)号：US20060024934A1

公开(公告)日：2006-02-02

申请号：US10710737

申请日：2004-07-30

申请人： Kevin Chan ,  Huajie Chen ,  Michael Gribelyuk ,  Judson Holt ,  Woo-Hyeong Lee ,  Ryan Mitchell ,  Renee Mo ,  Dan Mocuta ,  Werner Rausch ,  Paul Ronsheim ,  Henry Utomo

发明人： Kevin Chan ,  Huajie Chen ,  Michael Gribelyuk ,  Judson Holt ,  Woo-Hyeong Lee ,  Ryan Mitchell ,  Renee Mo ,  Dan Mocuta ,  Werner Rausch ,  Paul Ronsheim ,  Henry Utomo

IPC分类号： H01L21/22 ,  H01L21/331

CPC分类号： H01L21/28044 ,  H01L21/324

摘要： The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

摘要翻译： 本发明提供了一种用于延迟掺杂剂从第一材料层（通常为半导体）扩散到覆盖层或反之亦然的方法。 在本发明的方法中，通过在两层之间形成包含碳和氧的单层来延缓掺杂剂从第一半导体扩散到覆层中或反之亦然。 使用化学预处理方法在本发明中形成单层，其中使用包括碘和醇如甲醇的溶液。

公开(公告)号：US06749684B1

公开(公告)日：2004-06-15

申请号：US10250181

申请日：2003-06-10

申请人： Huajie Chen ,  Dan Mocuta ,  Richard J. Murphy ,  Paul Ronsheim ,  David Rockwell

发明人： Huajie Chen ,  Dan Mocuta ,  Richard J. Murphy ,  Paul Ronsheim ,  David Rockwell

IPC分类号： C30B2504

CPC分类号： C30B29/06 ,  C30B25/02 ,  C30B29/08 ,  C30B29/52

摘要： A method is disclosed for forming an epitaxial layer on a front side of a substrate formed of a monocrystalline material, using a chemical vapor deposition system. In this method, a plurality of gettering wafers formed of a gettering material are arranged in the CVD system, such that the front side of each substrate is facing one of the gettering wafers. Impurities present in the CVD system during formation of the epitaxial layer are gettered by the gettering wafers. Alternatively, a layer of a gettering material is deposited on a back side of each of the plurality of substrates, and the substrates are arranged such that the front side of each substrate is facing the backside of another of the substrates. In another embodiment, a layer of a gettering material is deposited on an interior surface of the CVD system. Impurities removed from the CVD system during epitaxial formation include oxygen, water vapor and other oxygen-containing contaminants.

摘要翻译： 公开了一种使用化学气相沉积系统在由单晶材料形成的基板的正面上形成外延层的方法。 在该方法中，在CVD系统中配置由吸气材料形成的多个吸气晶片，使得每个基板的前侧面对吸气晶片之一。 在形成外延层期间存在于CVD系统中的杂质被吸杂晶片吸收。 或者，在多个基板的每一个的背面上沉积吸气材料层，并且将基板布置成使得每个基板的前侧面对另一个基板的背面。 在另一个实施例中，吸气材料层沉积在CVD系统的内表面上。 在外延形成期间从CVD系统中除去的杂质包括氧，水蒸气和其它含氧污染物。

公开(公告)号：US20060292779A1

公开(公告)日：2006-12-28

申请号：US11463777

申请日：2006-08-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L21/8234

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

摘要翻译： 提供场效应晶体管（“FET”），其包括覆盖衬底的单晶半导体区域的栅极堆叠，设置在所述栅极堆叠的侧壁上的一对第一间隔区，以及基本上由单个 晶体半导体合金，其设置在栅叠层的相对侧上。 每个半导体合金区域与栅极叠层隔开第一距离。 FET的源极区域和漏极区域至少部分地设置在半导体合金区域的相应半导体合金区域中，使得源极区域和漏极区域之间的距离与栅极叠层间隔开第二距离， 第一间隔物，第二距离与第一距离不同。

公开(公告)号：US20060065914A1

公开(公告)日：2006-03-30

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

公开(公告)号：US20060151837A1

公开(公告)日：2006-07-13

申请号：US10905598

申请日：2005-01-12

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry Utomo ,  Werner Rausch

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Siddhartha Panda ,  Sang-Hyun Oh ,  Henry Utomo ,  Werner Rausch

IPC分类号： H01L29/94

CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.

摘要翻译： 公开了一种集成电路结构以及在衬底上具有衬底和P型和N型晶体管的结构的方法。 N型晶体管延伸和源极/漏极区域包括注入到衬底中的掺杂剂。 P型晶体管延伸和源极/漏极区域部分地包括应变外延硅锗，其中应变硅锗包括两层，顶层比底层更靠近栅极堆叠。 应变硅锗被原位掺杂并在沟道区域上产生纵向应力。

公开(公告)号：US20050148161A1

公开(公告)日：2005-07-07

申请号：US10751208

申请日：2004-01-02

申请人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephan Bedell ,  Devendra Sadana

发明人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephan Bedell ,  Devendra Sadana

IPC分类号： C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/36 ,  H01L21/44

CPC分类号： H01L21/02046 ,  C30B25/02 ,  C30B29/06 ,  C30B29/52 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02661 ,  Y10S438/933

摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves a first amount of oxygen (typically 1×1013-1×1015/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process which heats the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface sufficiently to remove additional oxygen from the surface and leave a second amount of oxygen, less than the first amount, on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The heating process leaves an amount of at least 5×1012/cm2 of oxygen (typically, between approximately 1×1013/cm2 and approximately 5×1013/cm2 of oxygen) on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. By leaving a small amount of oxygen on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

公开(公告)号：US20070128840A1

公开(公告)日：2007-06-07

申请号：US10597066

申请日：2004-01-16

申请人： Huajie Chen ,  Stephen Bedell ,  Devendra Sadana ,  Dan Mocuta

发明人： Huajie Chen ,  Stephen Bedell ,  Devendra Sadana ,  Dan Mocuta

IPC分类号： H01L21/20

CPC分类号： H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

摘要： A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.

摘要翻译： 一种形成绝缘体上硅锗（SGOI）结构的方法。 SiGe层沉积在SOI晶片上。 进行SiGe和Si层的热混合以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI。 然后将SiGe层变薄至所需的最终厚度。 稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。 因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。 然后在薄SGOI晶片上沉积一层Si。 稀释方法包括低温​​（550℃-700℃）HIPOX或蒸汽氧化，在外延室中进行原位HCl蚀刻或CMP。 由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑，或者在氢气环境中用HCl，DCS混合气体加热晶片 和GeH 4。

公开(公告)号：US07071103B2

公开(公告)日：2006-07-04

申请号：US10710737

申请日：2004-07-30

申请人： Kevin K. Chan ,  Huajie Chen ,  Michael A. Gribelyuk ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Ryan M. Mitchell ,  Renee T. Mo ,  Dan M. Mocuta ,  Werner A. Rausch ,  Paul A. Ronsheim ,  Henry K. Utomo

发明人： Kevin K. Chan ,  Huajie Chen ,  Michael A. Gribelyuk ,  Judson R. Holt ,  Woo-Hyeong Lee ,  Ryan M. Mitchell ,  Renee T. Mo ,  Dan M. Mocuta ,  Werner A. Rausch ,  Paul A. Ronsheim ,  Henry K. Utomo

IPC分类号： H01L21/44

CPC分类号： H01L21/28044 ,  H01L21/324

摘要： The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.

摘要翻译： 本发明提供了一种用于延迟掺杂剂从第一材料层（通常为半导体）扩散到覆盖层或反之亦然的方法。 在本发明的方法中，通过在两层之间形成包含碳和氧的单层来延缓掺杂剂从第一半导体扩散到覆层中或反之亦然。 使用化学预处理方法在本发明中形成单层，其中使用包括碘和醇如甲醇的溶液。

公开(公告)号：US20050148162A1

公开(公告)日：2005-07-07

申请号：US10751207

申请日：2004-01-02

申请人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephen Bedell ,  Devendra Sadana

发明人： Huajie Chen ,  Dan Mocuta ,  Richard Murphy ,  Stephen Bedell ,  Devendra Sadana

IPC分类号： C30B25/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/306 ,  H01L21/36 ,  H01L21/44

CPC分类号： H01L21/02046 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02052 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02661

摘要： The invention forms an epitaxial silicon-containing layer on a silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface and avoids creating a rough surface upon which the epitaxial silicon-containing layer is grown. In order to avoid creating the rough surface, the invention first performs a hydrofluoric acid etching process on the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. This etching process removes most of oxide from the surface, and leaves only a sub-monolayer of oxygen (typically 1×1013-1×1015/cm2 of oxygen) at the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. The invention then performs a hydrogen pre-bake process in a chlorine containing environment which heats the silicon germanium, strained silicon, or thin silicon-on-insulator surface sufficiently to remove the remaining oxygen from the surface. By introducing a small amount of chlorine containing gases, the heating processes avoid changing the roughness of the silicon germanium, patterned strained silicon, or patterned thin silicon-on-insulator surface. Then the process of epitaxially growing the epitaxial silicon-containing layer on the silicon germanium, patterned strained silicon, or patterned silicon-on-insulator surface is performed.

摘要翻译： 本发明在硅​​锗，图案化的应变硅或图案化的绝缘体上硅表面上形成外延含硅层，并避免产生外延含硅层生长的粗糙表面。 为了避免产生粗糙表面，本发明首先对硅锗，图案化应变硅或图案化的绝缘体上硅表面进行氢氟酸蚀刻工艺。 该蚀刻工艺从表面除去大部分氧化物，并且仅留下氧气的亚单层（通常为1×10 13/1×10 15 / cm 2以上） 的氧），图案化的应变硅或图案化的绝缘体上硅表面。 然后，本发明在含氯环境中进行氢预烘烤过程，其中充分加热硅锗，应变硅或薄的绝缘体上硅表面以从表面除去剩余的氧。 通过引入少量的含氯气体，加热过程避免改变硅锗，图案化的应变硅或图案化的绝缘体上硅表面的粗糙度。 然后进行外延生长硅锗，图案化应变硅或图案化硅绝缘体表面上的外延硅含量层的工艺。

公开(公告)号：US20060255330A1

公开(公告)日：2006-11-16

申请号：US10908394

申请日：2005-05-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Dominic Schepis ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Dominic Schepis ,  Henry Utomo

IPC分类号： H01L27/12 ,  H01L29/06

CPC分类号： H01L29/7842 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78684

摘要： Disclosed is a p-type field effect transistor (pFET) structure and method of forming the pFET. The pFET comprises embedded silicon germanium in the source/drain regions to increase longitudinal stress on the p-channel and, thereby, enhance transistor performance. Increased stress is achieved by increasing the depth of the source/drain regions and, thereby, the volume of the embedded silicon germanium. The greater depth (e.g., up to 100 nm) of the stressed silicon germanium source/drain regions is achieved by using a double BOX SOI wafer. Trenches are etched through a first silicon layer and first buried oxide layer and then the stressed silicon germanium is epitaxially grown from a second silicon layer. A second buried oxide layer isolates the pFET.

摘要翻译： 公开了一种形成pFET的p型场效应晶体管（pFET）结构和方法。 pFET在源极/漏极区域中包括嵌入的硅锗以增加p沟道上的纵向应力，从而增强晶体管的性能。 通过增加源极/漏极区域的深度，从而增加嵌入式硅锗的体积来实现增加的应力。 通过使用双BOX SOI晶片来实现应力硅锗源极/漏极区域的更大的深度（例如高达100nm）。 通过第一硅层和第一掩埋氧化物层蚀刻沟槽，然后从第二硅层外延生长受应力的硅锗。 第二掩埋氧化物层隔离pFET。