公开(公告)号：US5399389A

公开(公告)日：1995-03-21

申请号：US94337

申请日：1993-07-20

申请人： Konrad Hieber ,  Jasper Von Tomkewitsch ,  Oswald Spindler ,  Helmuth Treichel ,  Zvonimir Gabric ,  Alexander Gschwandtner

发明人： Konrad Hieber ,  Jasper Von Tomkewitsch ,  Oswald Spindler ,  Helmuth Treichel ,  Zvonimir Gabric ,  Alexander Gschwandtner

IPC分类号： C30B29/18 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  B05D3/06 ,  H01L21/02

CPC分类号： H01L21/02164 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/31612 ,  H01L21/76819

摘要： In the ozone-activated deposition of insulating layers, different growth rates can be achieved on differently constituted surfaces. When the surfaces of the structured silicon substrates lying at different levels are differently constituted or, respectively, are intentionally varied such that the SiO.sub.2 insulating layer grows more slowly on the higher surfaces than on the more deeply disposed surfaces and when deposition is carried out until the surfaces of the rapidly growing and slowly growing layer regions form a step-free, planar level, a local and global planarization is achieved.

摘要翻译： 在绝缘层的臭氧活化沉积中，可以在不同构造的表面上实现不同的生长速率。 当不同层次的结构硅衬底的表面被不同地构成或分别有意地改变，使得SiO 2绝缘层在较高表面上比在更深的设置表面上更缓慢地生长，并且当沉积被执行直到 快速生长和缓慢生长的层区域的表面形成无梯度的平面水平，实现局部和全局平坦化。

公开(公告)号：US5281302A

公开(公告)日：1994-01-25

申请号：US4528

申请日：1993-01-14

申请人： Zvonimir Gabric ,  Alexander Gschwandtner ,  Oswald Spindler

发明人： Zvonimir Gabric ,  Alexander Gschwandtner ,  Oswald Spindler

IPC分类号： C23F4/00 ,  C23C16/44 ,  C23G5/00 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31 ,  B44C1/22 ,  B29C37/00 ,  C03C15/00 ,  C03C25/06

CPC分类号： C23G5/00 ,  C23C16/4405

摘要： For cleaning parasitic layers of silicon oxides or nitrides in a reaction chamber, an etching gas mixture is employed in which at least one fluoridated carbon, particularly CF.sub.4 and/or C.sub.2 F.sub.6, is the main constituent. Then, an ozone/oxygen mixture (O.sub.3 /O.sub.2) having optimally high ozone concentration is added to the reaction chamber. The etching gas mixture is excited in the reaction chamber by triggering the etching gas mixture to form a plasma, having extremely low power with an excitation frequency in the RF range. The etching gas mixture etches all surfaces in the reaction chambers free of residues with a high etching rate.

摘要翻译： 为了清除反应室中的氧化硅或氮化物的寄生层，使用至少一种氟化碳，特别是CF 4和/或C 2 F 6作为主要成分的蚀刻气体混合物。 然后，将具有最高臭氧浓度的臭氧/氧气混合物（O 3 / O 2）加入到反应室中。 通过触发蚀刻气体混合物形成等离子体，在反应室中激发蚀刻气体混合物，其功率极低，在RF范围内具有激发频率。 蚀刻气体混合物以高蚀刻速率蚀刻反应室中没有残留物的所有表面。

公开(公告)号：US06429092B1

公开(公告)日：2002-08-06

申请号：US09596606

申请日：2000-06-19

申请人： Jochen Beintner ,  Alexander Michaelis ,  Ulrike Gruening ,  Oswald Spindler ,  Zvonimir Gabric

发明人： Jochen Beintner ,  Alexander Michaelis ,  Ulrike Gruening ,  Oswald Spindler ,  Zvonimir Gabric

IPC分类号： H01L2176

CPC分类号： H01L27/10861 ,  H01L21/31612 ,  H01L21/32 ,  H01L27/1087

摘要： A method for forming an oxide collar in a trench, in accordance with the present invention, includes forming a trench in a silicon substrate, and depositing and recessing a nitride liner in the trench to expose a portion of the silicon substrate on sidewalls of the trench. An oxide is deposited selective to the nitride liner on the portion of the silicon substrate. Residue oxide is removed from surfaces of the nitride liner to form a collar in the trench.

摘要翻译： 根据本发明的在沟槽中形成氧化物环的方法包括在硅衬底中形成沟槽，以及在沟槽中沉积和凹陷氮化物衬垫以暴露沟槽侧壁上的硅衬底的一部分 。 对硅衬底的部分上的氮化物衬垫选择性地沉积氧化物。 从氮化物衬垫的表面去除残余氧化物，以在沟槽中形成环。

公开(公告)号：US06380074B1

公开(公告)日：2002-04-30

申请号：US09666526

申请日：2000-09-18

申请人： Markus Kirchhoff ,  Hans-Peter Sperlich ,  Uwe Schilling ,  Zvonimir Gabric ,  Oswald Spindler ,  Stephan Wege ,  Hans Glawischnig

发明人： Markus Kirchhoff ,  Hans-Peter Sperlich ,  Uwe Schilling ,  Zvonimir Gabric ,  Oswald Spindler ,  Stephan Wege ,  Hans Glawischnig

IPC分类号： H01L214763

CPC分类号： H01L21/02129 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L21/76262

摘要： A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

摘要翻译： 描述了一种采用半导体电路中的无收缩空穴填充的方法，其利用被施加层的选择性生长。 在该方法中，选择性生长材料层同时施加到生长促进层和生长抑制层。 其中在施加选择性生长材料层之前至少在其侧面被生长抑制层覆盖的凸起部分。 在施加生长抑制层之后，通过各向异性处理在凸起部分之间和之间平行于衬底的表面产生生长促进层，然后再次在凸起部分上平行于衬底的表面上去除该层。 该方法使得可以以特别简单的方式产生其隆起部分上的生长抑制层在其侧面和顶部覆盖的图案，而沟槽的底部被生长促进层覆盖。

公开(公告)号：US5837611A

公开(公告)日：1998-11-17

申请号：US907210

申请日：1997-08-06

申请人： Zvonimir Gabric ,  Oswald Spindler ,  Thomas Grassl

发明人： Zvonimir Gabric ,  Oswald Spindler ,  Thomas Grassl

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/00

CPC分类号： H01L21/02164 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/31608 ,  H01L21/76819

摘要： When large-scale integrated circuits are produced, pronounced differences in height occur within conductor track levels. Those extreme topographies lead to difficulties during photo-lithographic processes, since there is a direct relationship between resolution and depth of focus. A production method for applying an insulation layer functioning as an intermetal dielectric is based on an ozone-activated selective deposition of silicon oxide. The conductor tracks are completely encapsulated with an insulation layer, so that bulges do not occur above upper edges of the conductor tracks.

摘要翻译： 当产生大规模集成电路时，高度的明显差异会在导体轨迹水平上发生。 这些极端的地形导致光刻过程中的困难，因为分辨率和焦点深度之间存在直接的关系。 作为金属间电介质发挥作用的绝缘层的制造方法是基于氧化硅的臭氧活化选择性沉积。 导体轨道被绝缘层完全封装，使得不会在导体轨道的上边缘之上发生凸起。

公开(公告)号：US06184091B2

公开(公告)日：2001-02-06

申请号：US09241756

申请日：1999-02-01

申请人： Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

发明人： Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

IPC分类号： H01L21336

CPC分类号： H01L27/10864 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L27/10876

摘要： A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

公开(公告)号：US5965203A

公开(公告)日：1999-10-12

申请号：US643599

申请日：1996-05-06

申请人： Zvonimir Gabric ,  Oswald Spindler

发明人： Zvonimir Gabric ,  Oswald Spindler

IPC分类号： C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/31 ,  H01L21/316 ,  C23C16/00

CPC分类号： C23C16/45523 ,  C23C16/402

摘要： A method for depositing a silicon oxide layer by ozone-activated gas phase deposition, uses tetraethyl orthosilicate (TEOS). An initially high gas flow ratio of TEOS to ozone is increasingly varied to a low steady-state ratio.

摘要翻译： 通过臭氧活化气相沉积法沉积氧化硅层的方法使用原硅酸四乙酯（TEOS）。 TEOS与臭氧的初始高气体流量比越来越多地变化到低的稳态比。

公开(公告)号：US06177698B1

公开(公告)日：2001-01-23

申请号：US09461599

申请日：1999-12-15

申请人： Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

发明人： Ulrike Gruening ,  Jochen Beintner ,  Dirk Tobben ,  Gill Lee ,  Oswald Spindler ,  Zvonimir Gabric

IPC分类号： H01L27108

CPC分类号： H01L27/10864 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/31612 ,  H01L27/10876

摘要： A method for controlling isolation layer thickness in trenches for semiconductor devices includes the steps of providing a trench having a conductive material formed therein, forming a liner on sidewalls of the trench above the conductive material, depositing a selective oxide deposition layer on the buried strap and the sidewalls, the selective oxide deposition layer selectively growing at an increased rate on the conductive material than on the liner of the sidewalls and top surface and removing the selective oxide deposition layer except for a portion in contact with the conductive to form an isolation layer on the conductive material in the trench. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.

摘要翻译： 用于控制用于半导体器件的沟槽中的隔离层厚度的方法包括以下步骤：提供在其中形成的导电材料的沟槽，在导电材料上方的沟槽的侧壁上形成衬垫，在掩埋带上沉积选择性氧化物沉积层， 侧壁，选择性氧化物沉积层以比在侧壁和顶表面的衬垫上更高的速率选择性地在导电材料上生长，并且除去与导电体接触的部分之外的选择性氧化物沉积层以形成隔离层 沟槽中的导电材料。 还包括当晶体管形成时，通过使衬底凹陷来制造垂直晶体管以允许晶体管沟道和掩埋带外扩散之间的重叠增加的方法。 还公开了一种半导体器件。

公开(公告)号：US20070120263A1

公开(公告)日：2007-05-31

申请号：US11506570

申请日：2006-08-18

申请人： Zvonimir Gabric ,  Werner Pamler ,  Guenther Schindler ,  Andreas Stich

发明人： Zvonimir Gabric ,  Werner Pamler ,  Guenther Schindler ,  Andreas Stich

IPC分类号： H01L23/48

CPC分类号： H01L21/7682

摘要： A conductor track arrangement includes a substrate, at least two conductor tracks, a cavity and a resist layer that covers the conductor tracks and closes off the cavity. By forming carrier tracks with a width less than a width of the conductor tracks, air gaps can also be formed laterally underneath the conductor tracks for reducing the coupling capacitances and the signal delays in a self-aligning manner.

摘要翻译： 导体轨道布置包括衬底，至少两个导体轨道，空腔和覆盖导体轨道并封闭空腔的抗蚀剂层。 通过形成宽度小于导体轨道的宽度的载体轨道，还可以在导体轨道下方横向形成气隙，以便以自对准方式减小耦合电容和信号延迟。

公开(公告)号：US06825098B2

公开(公告)日：2004-11-30

申请号：US10606069

申请日：2003-06-25

申请人： Zvonimir Gabric ,  Werner Pamler ,  Siegfried Schwarzl

发明人： Zvonimir Gabric ,  Werner Pamler ,  Siegfried Schwarzl

IPC分类号： H10L2130

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method referred to as a “cellular damascene method” utilizes a multiplicity of regularly arranged closed cavities referred to as “cells”, which are produced in a patterning layer. The dimensions of the cavities are on the order of magnitude of the microstructures to be produced. Selected cavities are opened by providing a mask and partitions situated between adjacent opened cavities are removed to provide trenches and holes which are filled with the material of the microstructure to be fabricated. Protruding material is removed by means of a chemical-mechanical polishing step. The microstructures are, in particular, interconnects and contact holes of integrated circuit.

摘要翻译： 称为“细胞镶嵌方法”的方法利用在图案化层中产生的多个规则排列的称为“单元”的闭合空腔。 空腔的尺寸在待生产的微结构的数量级上。 通过提供掩模来打开选定的空腔，并移除位于相邻的开放空腔之间的隔板，以提供用待制造的微结构材料填充的沟槽和孔。 通过化学机械抛光步骤去除突起材料。 微结构尤其是集成电路的互连和接触孔。