公开(公告)号：US20130268795A1

公开(公告)日：2013-10-10

申请号：US13729382

申请日：2012-12-28

申请人： Kumiko NOMURA ,  Shinobu FUJITA ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Hiroki NOGUCHI

发明人： Kumiko NOMURA ,  Shinobu FUJITA ,  Keiko ABE ,  Kazutaka IKEGAMI ,  Hiroki NOGUCHI

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

摘要： According to one embodiment, a cache system includes a tag memory includes a volatile memory device, the tag memory includes ways and storing a tag for each line, a data memory includes a nonvolatile memory device including sense amplifiers for reading data, the data memory includes ways and storing data for each line, a comparison circuit configured to compare a tag included in an address supplied from an external with a tag read from the tag memory, and a controller configured to turn off a power of a sense amplifier for a way which is not accessed based on a comparison result of the comparison circuit.

摘要翻译： 根据一个实施例，缓存系统包括标签存储器，其包括易失性存储器设备，标签存储器包括每条线路的方式和存储标签，数据存储器包括包括用于读取数据的读出放大器的非易失性存储器件，数据存储器包括 方式和存储每行的数据，比较电路，被配置为将从外部提供的地址中包含的标签与从标签存储器读取的标签进行比较，以及控制器，被配置为关闭读出放大器的功率， 基于比较电路的比较结果不被访问。

公开(公告)号：US20120246412A1

公开(公告)日：2012-09-27

申请号：US13234837

申请日：2011-09-16

申请人： Kumiko NOMURA ,  Keiko ABE ,  Shinobu FUJITA

发明人： Kumiko NOMURA ,  Keiko ABE ,  Shinobu FUJITA

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F12/123 ,  G06F2212/225 ,  Y02D10/13

摘要： According to an embodiment, in a cache system, the sequence storage stores sequence data in association with each piece of data to be stored in the volatile cache memory in accordance with the number of pieces of data stored in the nonvolatile cache memory that have been unused for a longer period of time than the data stored in the volatile cache memory or the number of pieces of data stored in the nonvolatile cache memory that have been unused for a shorter period of time than the data stored in the volatile cache memory. The controller causes the first piece of data to be stored in the nonvolatile cache memory in a case where it can be determined that the first piece of data has been unused for a shorter period of time than any piece of the data stored in the nonvolatile cache memory.

摘要翻译： 根据实施例，在高速缓存系统中，序列存储器根据存储在非易失性高速缓冲存储器中的数据的数量与已经被使用的非易失性高速缓冲存储器中存储的数据数量相关联地存储与要存储在易失性高速缓存存储器中的每条数据相关联 比存储在易失性高速缓冲存储器中的数据或存储在非易失性高速缓冲存储器中的数据的时间长于存储在易失性高速缓冲存储器中的数据的时间长于较短时间段的更长时间段。 在可以确定第一条数据已被使用的时间短于存储在非易失性高速缓冲存储器中的任何数据的时间段的情况下，控制器使得第一条数据被存储在非易失性高速缓冲存储器中 记忆。

公开(公告)号：US20120089656A1

公开(公告)日：2012-04-12

申请号：US13301932

申请日：2011-11-22

申请人： Tetsufumi TANAMOTO ,  Mari MATSUMOTO ,  Shinobu FUJITA ,  Kazutaka IKEGAMI

发明人： Tetsufumi TANAMOTO ,  Mari MATSUMOTO ,  Shinobu FUJITA ,  Kazutaka IKEGAMI

IPC分类号： G06F7/58

CPC分类号： H03K3/84 ,  G06F7/58

摘要： A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.

摘要翻译： 随机数生成电路包括：生成并输出物理随机数的元素; 数字化电路将物理随机数字化，以输出由测试电路测试的随机数序列; 以及纠错码电路，包括具有输入的随机数序列的移位寄存器，将所存储的随机数序列乘以纠错码生成矩阵的乘法器和输出移位寄存器的输出和 根据由测试电路获得的测试结果的乘数的输出。 当由测试电路执行的测试结果指示拒绝时，纠错码电路将来自选择器开关的乘法器的输出作为校正的随机数序列输出。 当测试结果表明拒绝时，测试电路测试校正的随机数序列。

公开(公告)号：US20110216573A1

公开(公告)日：2011-09-08

申请号：US12884452

申请日：2010-09-17

申请人： Keiko ABE ,  Shinobu FUJITA

发明人： Keiko ABE ,  Shinobu FUJITA

IPC分类号： G11C11/15 ,  G11C11/21

CPC分类号： G11C14/009 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/21 ,  G11C14/0054 ,  G11C14/0081

摘要： According to one embodiment, a semiconductor integrated circuit includes first and second inverters, a first transistor which has a gate connected to a word line, a source connected to a first bit line, and a drain connected to an input terminal of the second inverter, a second transistor which has a gate connected to the word line, a source connected to a second bit line, and a drain connected to an input terminal of the first inverter, a first variable resistive element which has a first terminal connected to the drain of the first transistor, and a second terminal connected to an output terminal of the first inverter, and a second variable resistive element which has a first terminal connected to the drain of the second transistor, and a second terminal connected to an output terminal of the second inverter.

摘要翻译： 根据一个实施例，半导体集成电路包括第一和第二反相器，具有连接到字线的栅极的第一晶体管，连接到第一位线的源极和连接到第二反相器的输入端子的漏极， 第二晶体管，其具有连接到字线的栅极，连接到第二位线的源极和连接到第一反相器的输入端子的漏极;第一可变电阻元件，其具有连接到第一位线的漏极的第一端子 第一晶体管和连接到第一反相器的输出端的第二端子，以及第二可变电阻元件，其具有连接到第二晶体管的漏极的第一端子，以及连接到第二晶体管的输出端子的第二端子 逆变器。

公开(公告)号：US20130028012A1

公开(公告)日：2013-01-31

申请号：US13556431

申请日：2012-07-24

申请人： Shinobu FUJITA ,  Keiko ABE

发明人： Shinobu FUJITA ,  Keiko ABE

IPC分类号： G11C11/16

CPC分类号： G11C14/0054 ,  G11C11/16 ,  G11C14/0081

摘要： In one embodiment, there is provided a semiconductor integrated circuit that includes: a first inverter; a second inverter; a first transistor, wherein one end of the first transistor is connected to a first bit line and the other end of the first transistor is connected to a first input terminal of the first inverter; a first element group including second transistors, wherein one end of the first element group is connected to a first output terminal of the first inverter and the other end of the first element group is connected to a second bit line; and a second element group including third transistors and a magnetoresistive element whose magnetic resistance is varied. The second element group is disposed between the second output terminal of the second inverter and a first terminal or disposed between the first transistor and the first terminal.

摘要翻译： 在一个实施例中，提供了一种半导体集成电路，其包括：第一反相器; 第二个逆变器; 第一晶体管，其中第一晶体管的一端连接到第一位线，第一晶体管的另一端连接到第一反相器的第一输入端; 包括第二晶体管的第一元件组，其中第一元件组的一端连接到第一反相器的第一输出端子，第一元件组的另一端连接到第二位线; 以及包括第三晶体管和磁阻变化的磁阻元件的第二元件组。 第二元件组设置在第二反相器的第二输出端子与第一端子之间或者设置在第一晶体管和第一端子之间。

公开(公告)号：US20120223440A1

公开(公告)日：2012-09-06

申请号：US13421115

申请日：2012-03-15

申请人： Shinobu FUJITA

发明人： Shinobu FUJITA

IPC分类号： H01L23/48 ,  H01L21/76

CPC分类号： H01L23/48 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/24 ,  H01L25/50 ,  H01L27/0688 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： In a three-dimensional integrated circuit apparatus 80 in which a first wafer 101 and a second wafer 102 having respective integrated circuits according to an embodiment are directly bonded, the second wafer 102 is provided with a through hole 10 aligned with a via 5a of the first wafer 101 by use of an alignment marker of the first wafer 101, and connected to the via 5a. The surrounding of the through hole 10 is provided with an insulating film 8.

摘要翻译： 在其中具有根据实施例的各个集成电路的第一晶片101和第二晶片102直接接合的三维集成电路装置80中，第二晶片102设置有与通孔5a对准的通孔10 第一晶片101，其通过使用第一晶片101的对准标记，并且连接到通孔5a。 通孔10的周围设有绝缘膜8。

公开(公告)号：US20120168290A1

公开(公告)日：2012-07-05

申请号：US13421314

申请日：2012-03-15

申请人： Shinobu FUJITA

发明人： Shinobu FUJITA

IPC分类号： H01H59/00

CPC分类号： H01H59/0009 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/16

摘要： According to one embodiment, a switch device includes a first switching unit provided on a base substance. The first switching unit includes a first supporting electrode, a first beam, a first contact point electrode, a first floating conductive layer and a first control electrode. The first supporting electrode is fixed to the base. The first beam includes a first holding part and a first movable part. The first holding part is fixed to the base. The first movable part has one end connected to the first holding part. The first contact point electrode is fixed to the base and faces the first movable part. The first floating conductive layer is fixed to the first movable part via a first insulating part and stores a charge. The first control electrode is fixed to the base and faces the first floating conductive layer.

摘要翻译： 根据一个实施例，开关装置包括设置在基础物质上的第一切换单元。 第一开关单元包括第一支撑电极，第一光束，第一接触点电极，第一浮动导电层和第一控制电极。 第一支撑电极固定在基座上。 第一梁包括第一保持部和第一可动部。 第一个保持部分固定在基座上。 第一可移动部分的一端连接到第一保持部分。 第一接触点电极固定在基座上，面向第一可移动部分。 第一浮动导电层经由第一绝缘部固定到第一可动部，并存储电荷。 第一控制电极固定到基座并且面向第一浮动导电层。

公开(公告)号：US20080241996A1

公开(公告)日：2008-10-02

申请号：US11860102

申请日：2007-09-24

申请人： Shinobu FUJITA

发明人： Shinobu FUJITA

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/28 ,  H01L24/31 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01016 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

摘要： A manufacturing method of a semiconductor device includes preparing a first semiconductor substrate having a first integrated circuit formed therein and including a plurality of first through substrate vias, and a second semiconductor substrate having a second integrated circuit formed therein and including a plurality of second through substrate vias, forming a solid-electrolytic layer on an upper surface of the first semiconductor substrate, mounting the second semiconductor substrate on the solid-electrolytic layer such that a lower surface of the second semiconductor substrate comes into contact with the solid-electrolytic layer, and applying a voltage between the plurality of first through substrate vias and the plurality of second through substrate vias, to form in the solid-electrolytic layer a plurality of connection electrodes, which are respectively connecting the plurality of second through substrate vias adjacent to the plurality of first through substrate vias to the plurality of first through substrate vias.

摘要翻译： 半导体器件的制造方法包括：制备具有形成在其中的第一集成电路的第一半导体衬底，并且包括多个第一贯通衬底通孔;以及第二半导体衬底，其具有形成在其中的第二集成电路，并且包括多个第二穿透衬底 通孔，在所述第一半导体衬底的上表面上形成固体电解质层，将所述第二半导体衬底安装在所述固体电解质层上，使得所述第二半导体衬底的下表面与所述固体电解质层接触;以及 在所述多个第一至第二基板通孔和所述多个第二贯穿基板通孔之间施加电压，以在所述固体电解质层中形成多个连接电极，所述多个连接电极分别连接所述多个第二贯穿基板通孔 首先通过基底通孔到达普拉 首先通过衬底通孔。

公开(公告)号：US20120250399A1

公开(公告)日：2012-10-04

申请号：US13403308

申请日：2012-02-23

申请人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

发明人： Hideyuki SUGIYAMA ,  Masato ODA ,  Shinobu FUJITA ,  Tetsufumi TANAMOTO ,  Mizue ISHIKAWA ,  Takao MARUKAME ,  Tomoaki INOKUCHI ,  Yoshiaki SAITO

IPC分类号： G11C11/16 ,  H03K19/177

CPC分类号： G11C5/148 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A memory circuit according to an embodiment includes: a first transistor including a first source/drain electrode, a second source/drain electrode, and a first gate electrode; a second transistor including a third source/drain electrode connected to the second source/drain electrode, a fourth source/drain electrode, and a second gate electrode; a third transistor and a fourth transistor forming an inverter circuit, the third transistor including a fifth source/drain electrode, a sixth source/drain electrode, and a third gate electrode connected to the second source/drain electrode, the fourth transistor including a seventh source/drain electrode connected to the sixth source/drain electrode, an eighth source/drain electrode, and a fourth gate electrode connected to the second source/drain electrode; and an output terminal connected to the sixth source/drain electrode. At least one of the third transistor and the fourth transistor is a spin MOSFET, and an output of the inverter circuit is sent from the output terminal.

摘要翻译： 根据实施例的存储器电路包括：第一晶体管，包括第一源极/漏极，第二源极/漏极和第一栅电极; 第二晶体管，包括连接到第二源极/漏极的第三源极/漏极，第四源极/漏极和第二栅极; 第三晶体管和形成逆变器电路的第四晶体管，所述第三晶体管包括第五源极/漏极，第六源极/漏极和连接到所述第二源极/漏极的第三栅电极，所述第四晶体管包括第七 连接到第六源极/漏极的源极/漏极电极，连接到第二源极/漏极的第八源极/漏极电极和第四栅极电极; 以及连接到第六源极/漏极的输出端子。 第三晶体管和第四晶体管中的至少一个是自旋MOSFET，并且从输出端子发送反相器电路的输出。

公开(公告)号：US20120243336A1

公开(公告)日：2012-09-27

申请号：US13240087

申请日：2011-09-22

申请人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

发明人： Yoshifumi NISHI ,  Daisuke HAGISHIMA ,  Shinichi YASUDA ,  Tetsufumi TANAMOTO ,  Takahiro KURITA ,  Atsuhiro KINOSHITA ,  Shinobu FUJITA

IPC分类号： G11C16/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。