公开(公告)号：US06995396B2

公开(公告)日：2006-02-07

申请号：US10279119

申请日：2002-10-24

申请人： Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kenya Yamashita ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kenya Yamashita ,  Ryoko Miyanaga

IPC分类号： H01L31/0312 ,  H01L29/80 ,  H01L31/112 ,  H01L29/76 ,  H01L27/095

CPC分类号： H01L29/365 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02584 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/0445 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC bulk substrate whose top face has been flattened is placed in a vertical thin film growth system to be annealed in an inert gas atmosphere. A material gas of Si is then supplied at a flow rate of 1 mL/min. at a substrate temperature of 1200° C. through 1600° C. Subsequently, the diluent gas is changed to a hydrogen gas at a temperature of 1600° C., and material gases of Si and carbon are supplied with nitrogen intermittently supplied, so as to deposit SiC thin films on the SiC bulk substrate. In a flat δ-doped multilayered structure thus formed, an average height of macro steps formed on the top face and on interfaces therein is 30 nm or less. When the resultant substrate is used, a semiconductor device with a high breakdown voltage and high mobility can be realized.

公开(公告)号：US06940127B2

公开(公告)日：2005-09-06

申请号：US10631086

申请日：2003-07-31

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

IPC分类号： H01L21/82 ,  H01L27/06 ,  H01L29/10 ,  H01L29/15 ,  H01L29/24 ,  H01L29/36 ,  H01L29/772 ,  H01L29/812 ,  H01L29/872 ,  H03D7/12 ,  H03F3/60 ,  H01L29/76

CPC分类号： H03F3/601 ,  H01L21/8213 ,  H01L27/0605 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/812 ,  H01L29/872 ,  H03D7/125 ,  H03F2200/294

摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of δ-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of δ-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the δ-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.

摘要翻译： 用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。 第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。 第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。 由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

公开(公告)号：US06504176B2

公开(公告)日：2003-01-07

申请号：US09824922

申请日：2001-04-03

申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi

发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi

IPC分类号： H01L310317

CPC分类号： H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7813

摘要： There are provided a field effect transistor with a high withstand voltage and low loss and a method of manufacturing the same. The field effect transistor includes an n-type substrate, an n-type semiconductor layer formed on the n-type substrate, a p-type semiconductor layer formed on the n-type semiconductor layer, a p-type region embedded in the n-type semiconductor layer, an n-type region embedded in the n-type semiconductor layer and the p-type semiconductor layer, an n-type source region disposed in the p-type semiconductor layer on its surface side, an insulating layer disposed on the p-type semiconductor layer, a gate electrode disposed on the insulating layer, a source electrode, and a drain electrode. The n-type semiconductor layer, the p-type semiconductor layer, and the p-type region are made of wide-gap semiconductors with a bandgap of at least 2 eV, respectively.

摘要翻译： 提供具有高耐受电压和低损耗的场效应晶体管及其制造方法。 场效应晶体管包括n型衬底，形成在n型衬底上的n型半导体层，形成在n型半导体层上的p型半导体层，嵌入在n型衬底中的p型区域， 埋入n型半导体层和p型半导体层的n型区域，在其表面侧配置在p型半导体层中的n型源极区域，设置在p型半导体层上的绝缘层 p型半导体层，设置在绝缘层上的栅电极，源电极和漏电极。 n型半导体层，p型半导体层和p型区域分别由具有至少2eV的带隙的宽间隙半导体制成。

公开(公告)号：US06900483B2

公开(公告)日：2005-05-31

申请号：US10162503

申请日：2002-06-04

申请人： Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Ryoko Miyanaga ,  Kenya Yamashita

发明人： Masao Uchida ,  Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Ryoko Miyanaga ,  Kenya Yamashita

IPC分类号： H01L21/329 ,  H01L29/24 ,  H01L29/872 ,  H01L29/80

CPC分类号： H01L29/66143 ,  H01L29/1608 ,  H01L29/872

摘要： A Schottky diode includes a semiconductor substrate made of 4H—SiC, an epitaxially grown 4H—SiC layer, an ion implantation layer, a Schottky electrode, an ohmic electrode, and an insulative layer made of a thermal oxide film. The Schottky electrode and the insulative layer are not in contact with each other, with a gap being provided therebetween, whereby an altered layer does not occur. Therefore, it is possible to suppress the occurrence of a leak current.

摘要翻译： 肖特基二极管包括由4H-SiC制成的半导体衬底，外延生长的4H-SiC层，离子注入层，肖特基电极，欧姆电极和由热氧化膜制成的绝缘层。 肖特基电极和绝缘层彼此不接触，其间设置有间隙，由此不发生改变的层。 因此，可以抑制泄漏电流的发生。

公开(公告)号：US06654604B2

公开(公告)日：2003-11-25

申请号：US09989270

申请日：2001-11-20

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto

IPC分类号： H04Q720

CPC分类号： H03F3/601 ,  H01L21/8213 ,  H01L27/0605 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/812 ,  H01L29/872 ,  H03D7/125 ,  H03F2200/294

摘要： Equipment for a communication system has a semiconductor device formed by integrating a Schottky diode, a MOSFET, a capacitor, and an inductor in a SiC substrate. The SiC substrate has a first multilayer portion and a second multilayer portion provided upwardly in this order. The first multilayer portion is composed of &dgr;-doped layers each containing an n-type impurity (nitrogen) at a high concentration and undoped layers which are alternately stacked. The second multilayer portion is composed of &dgr;-doped layers each containing a p-type impurity (aluminum) at a high concentration and undoped layers which are alternately stacked. Carriers in the &dgr;-doped layers spread out extensively to the undoped layers. Because of a low impurity concentration in each of the undoped layers, scattering by impurity ions is reduced so that a low resistance and a high breakdown voltage are obtained.

摘要翻译： 用于通信系统的设备具有通过将肖特基二极管，MOSFET，电容器和电感器集成在SiC衬底中而形成的半导体器件。 SiC衬底具有依次向上设置的第一多层部分和第二多层部分。 第一多层部分由各自含有高浓度的n型杂质（氮）和交替层叠的未掺杂层的δ掺杂层组成。 第二多层部分由各自含有高浓度的p型杂质（铝）和交替层叠的未掺杂层的δ掺杂层组成。 δ掺杂层中的载体广泛扩展到未掺杂的层。 由于每个未掺杂的层中的杂质浓度低，所以杂质离子的散射被降低，从而获得低的电阻和高的击穿电压。

公开(公告)号：US06600203B2

公开(公告)日：2003-07-29

申请号：US10127126

申请日：2002-04-22

申请人： Kunimasa Takahashi ,  Toshiya Yokogawa ,  Makoto Kitabatake ,  Masao Uchida ,  Osamu Kusumoto ,  Kenya Yamashita

发明人： Kunimasa Takahashi ,  Toshiya Yokogawa ,  Makoto Kitabatake ,  Masao Uchida ,  Osamu Kusumoto ,  Kenya Yamashita

IPC分类号： H01L3100

CPC分类号： H01L29/7813 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L29/0878 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1075 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/812 ,  H01L29/872

摘要： A suppression layer is formed on a SiC substrate in accordance with a CVD method which alternately repeats the step of epitaxially growing an undoped layer which is a SiC layer into which an impurity is not introduced and the step of epitaxially growing an impurity doped layer which is a SiC layer into which nitrogen is introduced pulsatively. A sharp concentration profile of nitrogen in the suppression layer prevents the extension of micropipes. A semiconductor device properly using the high breakdown voltage and high-temperature operability of SiC can be formed by depositing SiC layers forming an active region on the suppression layer.

摘要翻译： 根据CVD方法，在SiC衬底上形成抑制层，该方法交替重复外延生长未引入杂质的SiC层的未掺杂层的步骤，以及外延生长杂质掺杂层的步骤 其中氮脉冲地引入其中的SiC层。 抑制层中氮的浓度曲线锐利，防止了微管的延伸。 可以通过在抑制层上沉积形成有源区的SiC层来形成适当地使用SiC的高击穿电压和高温可操作性的半导体器件。

公开(公告)号：US06580125B2

公开(公告)日：2003-06-17

申请号：US10204097

申请日：2002-08-15

申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L2976

CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

摘要： A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.

摘要翻译： DMOS器件（或IGBT）包括SiC衬底2，形成在外延层中的n-SiC层3（漂移区），栅极绝缘膜6，栅电极7a，形成为围绕栅电极的源电极7b 如图7a所示，形成在SiC衬底2的下表面上的漏极电极7c，形成为从源电极7b的下边缘形成的p-SiC层4，n + SiC层3到栅电极7a的相关边缘 。 此外，该器件包括含有高浓度氮的n型掺杂层10a和未掺杂层10b，层叠在除了形成n + SiC层5的区域之外的外延层的表面部分的区域中 。 通过利用量子效应，器件可以使其导通电阻降低，并且当其处于截止状态时也可以使其击穿电压增加。

公开(公告)号：US06306211B1

公开(公告)日：2001-10-23

申请号：US09523671

申请日：2000-03-10

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Masao Uchida ,  Toshiya Yokogawa

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Masao Uchida ,  Toshiya Yokogawa

IPC分类号： C30B2514

CPC分类号： H01L29/66068 ,  C30B25/02 ,  C30B25/14 ,  C30B29/52 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02658 ,  H01L21/0455 ,  H01L29/365 ,  H01L29/66431

摘要： In a chamber, a substrate is mounted on a susceptor and then heated to an elevated temperature. Source and diluting gases are supplied into the chamber through source and diluting gas supply pipes provided with respective flow meters. In addition, a doping gas is also supplied through an additive gas supply pipe, which is provided with a pulse valve, and a gas inlet pipe into the chamber by repeatedly opening and closing the pulse valve. In this manner, a doped layer is grown epitaxially on the substrate. In this case, a pulsed flow of the doping gas is directly supplied through the pulse valve onto the substrate from the outlet port of a pressure reducer for a doping gas cylinder. As a result, a steeply rising dopant concentration profile appears in a transition region between the substrate and the doped layer, and the surface of the doped layer is planarized.

摘要翻译： 在室中，将基底安装在基座上，然后加热到升高的温度。 源和稀释气体通过源和稀释供应有相应流量计的气体供应管道供应到室中。 此外，还通过反复打开和关闭脉冲阀，通过设置有脉冲阀的添加剂气体供给管和进入管中的气体导入管来供给掺杂气体。 以这种方式，在衬底上外延生长掺杂层。 在这种情况下，掺杂气体的脉冲流通过脉冲阀从用于掺杂气体筒的减压器的出口直接供给到基板上。 结果，在衬底和掺杂层之间的过渡区域中出现急剧上升的掺杂剂浓度分布，并且掺杂层的表面被平坦化。

公开(公告)号：US07846828B2

公开(公告)日：2010-12-07

申请号：US12338395

申请日：2008-12-18

申请人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

发明人： Osamu Kusumoto ,  Makoto Kitabatake ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita ,  Masahiro Hagio ,  Kazuyuki Sawada

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L29/7828 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/30625 ,  H01L29/1029 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/812

摘要： Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability.

摘要翻译： 进行离子注入以在SiC衬底上的高电阻SiC层的部分中形成p阱区域和源极区域，并且在衬底上沉积碳膜。 通过沉积在基板上的碳膜，进行用于激活注入的掺杂离子的退火，然后除去碳膜。 因此，获得了退火几乎没有表面粗糙度的光滑表面。 此外，如果沟道层外延生长，则沟道层的表面粗糙度小于下层的表面粗糙度。 由于提供了具有平滑表面的沟道层，所以可以获得具有高电流驱动能力的MISFET。

公开(公告)号：US07462540B2

公开(公告)日：2008-12-09

申请号：US10553845

申请日：2005-01-28

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Kenya Yamashita ,  Masao Uchida ,  Osamu Kusumoto ,  Ryoko Miyanaga

IPC分类号： H01L21/00

CPC分类号： H01L21/046

摘要： A method for fabricating a semiconductor device includes the steps of implanting ions into a silicon carbide thin film (2) formed on a silicon carbide substrate (1), heating the silicon carbide substrate in a reduced pressure atmosphere to form a carbon layer (5) on the surface of the silicon carbide substrate, and performing activation annealing with respect to the silicon carbide substrate in an atmosphere under a pressure higher than in the step of forming the carbon layer (5) and at a temperature higher than in the step of forming the carbon layer (5).

摘要翻译： 一种制造半导体器件的方法包括以下步骤：将离子注入形成在碳化硅衬底（1）上的碳化硅薄膜（2）中，在减压气氛中加热碳化硅衬底以形成碳层（5） 在碳化硅衬底的表面上，并且在比形成碳层（5）的步骤高的压力的气氛中，并且在高于形成步骤的温度的气氛中，相对于碳化硅衬底进行激活退火 碳层（5）。