Substrate processing system with tandem source activation for CVD

    公开(公告)号:US11434567B2

    公开(公告)日:2022-09-06

    申请号:US16806560

    申请日:2020-03-02

    摘要: A substrate processing system includes a first power source configured to supply plasma having a first power level, a second power source configured to supply plasma having a second power level greater than the first power level, and a controller configured to dose a process chamber with precursor. The first power level is sufficient to enhance adsorption of the precursor on a surface of a substrate and is insufficient to decompose the precursor that is adsorbed. The controller is further configured to remove a portion of the precursor that does not adsorb onto the substrate from the process chamber while the plasma having the first power level is being supplied and activate the precursor that is adsorbed using plasma having the second power level while the plasma having the first power level is still being supplied. The second power level is sufficient to decompose the precursor that is adsorbed.

    Controller for Controlling Core Critical Dimension Variation Using Flash Trim Sequence

    公开(公告)号:US20200350219A1

    公开(公告)日:2020-11-05

    申请号:US16935137

    申请日:2020-07-21

    摘要: A pattern of core material is formed on a wafer to include core features that have a critical dimension. A trim amount indicates an average amount of thickness to be removed from vertically oriented surfaces of the core features. A trim profile indicates how much variation in removal of thickness from vertically oriented surfaces of the core features is to be applied as a function of radial location on the wafer. A first set of data correlates the trim amount to one or more plasma trim process parameters. A second set of data correlates the trim profile to one or more plasma trim process parameters. Based on the trim amount, trim profile, and first and second sets of data, a set of plasma trim process parameters to achieve the trim amount and trim profile on the wafer is determined and a corresponding plasma trim process is performed on the wafer.