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    SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT
    7.
    发明申请
    SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT 审中-公开
    自组装材料模式转移对比增强

    公开(公告)号：US20090117360A1

    公开(公告)日：2009-05-07

    申请号：US11933760

    申请日：2007-11-01

    申请人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

    发明人： Lawrence A. Clevenger ,  Timothy J. Dalton ,  Habib Hichri ,  Louis L. Hsu ,  Kaushik A. Kumar ,  Carl Radens ,  Shahab Siddiqui ,  Chih-Chao Yang

    IPC分类号： G03C1/73 ,  B05D3/00 ,  B32B27/06

    CPC分类号： H01L21/0337 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y30/00 ,  H01L21/0338

    摘要： A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region.

    摘要翻译： 含有至少两个不混溶的聚合物嵌段组分的非光敏聚合物抗蚀剂沉积在平面上。 将非光敏聚合物抗蚀剂退火以允许不相容组分的相分离并显影以除去至少两种聚合物嵌段组分中的至少一种。 在聚合物抗蚀剂中形成纳米尺度特征，即纳米尺度的特征，包括具有纳米级尺寸的至少一个凹陷区域。 聚合物抗蚀剂的顶表面通过暴露于能量束而被改进以提高耐蚀刻性，这允许图案化聚合物抗蚀剂的顶表面变得更耐蚀刻工艺和化学物质。 两种类型表面之间的增强的耐蚀刻比提供了改善的图像对比度和具有顶表面和至少一个凹陷区域的区域之间的保真度。

    Patterning microelectronic features without using photoresists
    8.
    发明授权
    Patterning microelectronic features without using photoresists 失效
    图案化微电子特征，而不使用光致抗蚀剂

    公开(公告)号：US06452110B1

    公开(公告)日：2002-09-17

    申请号：US09897889

    申请日：2001-07-05

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Keith Kwong Hon Wong

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Keith Kwong Hon Wong

    IPC分类号： H05K109

    CPC分类号： H05K3/02 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/76885 ,  Y10T29/49155 ,  Y10T29/49156

    摘要： A method and structure for producing metallic polymer conductor lines comprising of an alternative methodology to a traditional damascene approach, called a cloisonne or inverse damascene approach. The cloisonne approach comprises the steps of coating a photosensitive polymer such as pyrrole or aniline with a silver salt on a semiconductor substrate. Using standard photolithography and resist developing techniques, the conducting polymer is exposed to a wet chemical developer, removing a portion of the exposed conducting polymer region, leaving only conducting polymer lines on top of the substrate. Next, an insulating dielectric layer is deposited over the entire structure and a chemical mechanical polish planarization of the insulator is performed creating the conducting polymer lines. Included in another aspect of the invention is a method and structure for a self-planarizing interconnect material comprising a conductive polymer thereby reducing the number of processing steps relative to the prior art.

    摘要翻译： 一种用于生产金属聚合物导体线的方法和结构，其包括传统大马士革方法的替代方法，称为景泰蓝或逆大马士革方法。 景泰蓝方法包括在半导体衬底上用银盐将光敏聚合物如吡咯或苯胺涂覆的步骤。 使用标准光刻和抗蚀显影技术，将导电聚合物暴露于湿化学显影剂，除去暴露的导电聚合物区域的一部分，仅在基底顶部留下导电聚合物线。 接下来，在整个结构上沉积绝缘电介质层，并进行绝缘体的化学机械抛光平面化，产生导电聚合物线。 包括在本发明的另一方面中的是一种用于自平坦化互连材料的方法和结构，其包括导电聚合物，从而减少相对于现有技术的加工步骤的数量。

    SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR
    9.
    发明申请
    SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR 有权
    半导体金属氧化物半导体场效应晶体管

    公开(公告)号：US20090212341A1

    公开(公告)日：2009-08-27

    申请号：US12034899

    申请日：2008-02-21

    申请人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

    发明人： Kangguo Cheng ,  Lawrence A. Clevenger ,  Timothy J. Dalton ,  Louis L. Hsu ,  Jack A. Mandelman

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/10826 ,  H01L29/66795 ,  H01L29/7841 ,  H01L29/7853

    摘要： An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure.

    摘要翻译： 在衬底上的多孔硅部分的外侧壁上形成硅锗合金层和外延应变硅层的外延半导体层或叠层。 去除多孔硅部分和任何硅锗合金材料，并形成三壁结构的半管状外延半导体结构。 在半管外延半导体结构上形成包括内栅电介质层和外栅电介质层，内栅电极，外栅电极以及源极和漏极区的半管场效应晶体管。 半管场效应晶体管可以作为具有通过内部和外部栅极电极的更严格的沟道控制的SOI晶体管，或作为在半管外延半导体结构内的体区中存储电荷的存储器件。

    Method and structure for providing improved thermal conduction for silicon semiconductor devices
    10.
    发明授权
    Method and structure for providing improved thermal conduction for silicon semiconductor devices 失效

    公开(公告)号：US07052937B2

    公开(公告)日：2006-05-30

    申请号：US10429758

    申请日：2003-05-05

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.