摘要:
A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
摘要:
A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.
摘要:
A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses. Because the major interior apertures does not need to be large enough to fit both the monolithic integrated circuit and the secondary circuit structure, there is more stiffener material available to provide structural support than there would be if the major interior aperture was large enough to fit both the monolithic integrated circuit and the secondary circuit structure.
摘要:
A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.
摘要:
A structure for receiving electrical signals near a central portion of the structure and distributing the electrical signals to a peripheral portion of the structure. The structure has a first set of contacts arranged in an array near the central portion of the structure. Electrically conductive traces connect the first set of contacts to a second set of contacts, where each of the electrically conductive traces has at least a first segment, a second segment, and a third segment. The first segment of each of the electrically conductive traces has relatively narrow width and spacing. The first segment of each of the electrically conductive traces is connected on a first end of the first segment to one of the first set of contacts and on a second end of the first segment to the second segment of each of the electrically conductive traces. The second segment of each of the electrically conductive traces has relatively intermediate width and spacing. The second segment of each of the electrically conductive traces is connected on a first end of the second segment to the second end of the first segment and on a second end of the second segment to the third segment of each of the electrically conductive traces. The third segment of each of the electrically conductive traces has relatively wide width and spacing. The third segment of each of the electrically conductive traces is connected on a first end of the third segment to the second end of the second segment and on a second end of the third segment to one of the second set of contacts.
摘要:
A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.
摘要:
A pattern of contacts that includes high speed transmitter contacts disposed in a first portion of the pattern, where the high speed transmitter contacts are disposed in transmitter differential pairs. High speed receiver contacts are disposed in a second portion of the pattern, where the first portion of the pattern is not interspersed with the second portion of the pattern, and the high speed receiver contacts are disposed in receiver differential pairs. At least one unbroken line of other contacts is disposed between the first portion of the pattern and the second portion of the pattern, where the other contacts do not contain any high speed transmitter contacts and high speed receiver contacts. Low speed IO contacts are disposed in a third portion of the pattern, where the third portion of the pattern is disposed in an interior portion of the pattern relative to both the first portion of the pattern and the second portion of the pattern. Substantially all of the contacts are disposed at a standard pitch one from another on a single contact surface.
摘要:
An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.
摘要:
The present invention provides a transmission equalization system for use with an integrated circuit package employing a substrate. In one embodiment, the transmission equalization system includes a signal transmission subsystem having a pair of transmission line conductors located in the substrate and employing a differential electrical signal. The transmission equalization system also includes an equalization subsystem located proximate the pair of transmission line conductors that employs at least one aperture positioned and oriented to provide a substantially equivalent transmission environment for each of the pair of transmission line conductors.
摘要:
The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.