公开(公告)号：US5065361A

公开(公告)日：1991-11-12

申请号：US446003

申请日：1989-12-05

申请人： Makoto Yoshizawa ,  Tadashi Maruyama

发明人： Makoto Yoshizawa ,  Tadashi Maruyama

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/08 ,  G11C16/30

CPC分类号： G11C16/08 ,  G11C16/30

摘要： A semiconductor memory integrated circuit is made up of a decoder, a memory matrix, and a decode output buffer selectively receiving a first or second power source voltage. The decode output buffer is provided between the decoder and the memory matrix, and includes an inverter circuit for inverting the output signal of the decoder, and a MOS transistor of a depletion mode, the gate of which is connected to the output terminal of the inverter, the first end of which is connected to a supply node of the first or second power source voltage, and the second end of which is connected to a power voltage supply node of the inverter circuit.

公开(公告)号：US4912749A

公开(公告)日：1990-03-27

申请号：US149606

申请日：1988-01-28

申请人： Tadashi Maruyama ,  Yukio Wada ,  Tomohisa Shigematsu ,  Yasoji Suzuki ,  Makoto Yoshizawa

发明人： Tadashi Maruyama ,  Yukio Wada ,  Tomohisa Shigematsu ,  Yasoji Suzuki ,  Makoto Yoshizawa

IPC分类号： G11C17/00 ,  B42D15/02 ,  B42D15/10 ,  G03H1/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0433 ,  G11C16/10

摘要： In a nonvolatile semiconductor memory according to the invention, a power source voltage of 5 V used in an ordinary read mode is applied to a read line in the data read mode without changing its value. If a write line, a selection gate line, a control gate line, and a read line are respectively set at 0 V, 5 V, 0 V, and 5 V in the data read mode, the potential at an n-type diffusion layer becomes 0 V. In this case, the potential at the control gate line is 0 V, and the potential at a floating gate electrode becomes substantially 0 V. That is, an electric field is not applied to a thin insulating film located between the floating gate electrode and the n-type diffusion layer. As a result, electron injection and discharge due to the tunnel effect do not occur.

公开(公告)号：US5040147A

公开(公告)日：1991-08-13

申请号：US494318

申请日：1990-03-16

申请人： Makoto Yoshizawa ,  Katsuaki Mohri ,  Takeshi Nakashiro ,  Tadashi Maruyama

发明人： Makoto Yoshizawa ,  Katsuaki Mohri ,  Takeshi Nakashiro ,  Tadashi Maruyama

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0433 ,  G11C16/26 ,  H01L29/7883

摘要： A nonvolatile semiconductor memory is a programmable and erasable nonvolatile semiconductor memory including a semiconductor substrate of a first conductivity type, source and drain diffusion layers in the semiconductor substrate, and a channel region between the source and drain diffusion layers. A first insulation film is continuously on the channel region and the drain diffusion layer adjacent to the channel region, and a floating gate layer is on the first insulation film. Further, a second insulation film having a thin film portion which is thinner than the first insulation film is on the floating gate layer, and a control gate layer is on the second insulation film.

公开(公告)号：US4870615A

公开(公告)日：1989-09-26

申请号：US150290

申请日：1988-01-29

申请人： Tadashi Maruyama ,  Yukio Wada ,  Tomohisa Shigematsu ,  Yasoji Suzuki ,  Makoto Yoshizawa

发明人： Tadashi Maruyama ,  Yukio Wada ,  Tomohisa Shigematsu ,  Yasoji Suzuki ,  Makoto Yoshizawa

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L27/115

CPC分类号： H01L27/115 ,  G11C16/0433

摘要： A nonvolatile semiconductor memory device comprises a cell transistor formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer, a first selecting transistor formed of an MOS transistor, whose gate is connected to a read gate line layer, whose source-drain path is connected at one end to a read line layer, and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor formed of an MOS transistor, whose gate is connected to a write gate line layer, whose source-drain path is connected at one end to a write line layer, and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage of 5 V can be supplied to the read line layer in the read mode.

公开(公告)号：US5580658A

公开(公告)日：1996-12-03

申请号：US273769

申请日：1994-07-12

申请人： Tadashi Maruyama ,  Katuhide Nagaoka ,  Masaki Okada

发明人： Tadashi Maruyama ,  Katuhide Nagaoka ,  Masaki Okada

IPC分类号： C22C47/16 ,  C04B35/52 ,  C04B35/80 ,  C04B35/83 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C22C32/00 ,  C22C47/00 ,  C22C47/06 ,  C22C47/08 ,  C22C47/18 ,  C22C49/00 ,  C22C49/02 ,  C22C49/14 ,  C22C101/10 ,  C23C16/04 ,  C23C16/26 ,  G21B1/11 ,  G21B1/17 ,  B32B9/00

CPC分类号： C04B41/009 ,  C04B35/83 ,  C04B41/5127 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C22C32/0089 ,  C22C47/06 ,  C22C47/08 ,  C22C49/14 ,  C23C16/045 ,  C23C16/26 ,  B22F2998/00 ,  B22F2998/10 ,  C04B2111/00405 ,  Y10T428/24942 ,  Y10T428/249956 ,  Y10T428/30

摘要： A function ally gradient composite material containing copper and carbon as main components and having a predetermined shape, in which the composition ratio of the copper to the carbon in the material continuously varies in at least one predetermined direction. The material is manufactured, for example, by impregnating carbon felt with a resin and thermo-compressively molding the impregnated felt (step S101), carbonizing the resin by baking (step S102) to provide a preformed carbon material (step S104). Pyrolytic carbon is thereafter deposited in the preformed carbon material by the CVI method (step S105) to provide a carbon material having the bulk density varying in a predetermined direction (step S107). After the wettability of the carbon material against copper is improved by siliconization (step S108), pores of the carbon material are impregnated with copper (step S109) to obtain a functionally gradient composite material of copper and carbon.

摘要翻译： 一种以铜和碳为主要成分并具有预定形状的功能性粘合梯度复合材料，其中材料中铜与碳的组成比在至少一个预定方向上连续变化。 该材料例如通过用树脂浸渍碳毡并热浸模塑浸渍的毡（步骤S101），通过烘烤碳化树脂（步骤S102）以制备预成型碳材料来制造（步骤S104）。 然后通过CVI方法将热解碳沉积在预成型碳材料中（步骤S105），以提供堆积密度在预定方向上变化的碳材料（步骤S107）。 在通过硅化改善碳材料对铜的润湿性（步骤S108）后，用铜浸渍碳材料的孔（步骤S109），得到铜和碳的功能梯度复合材料。

公开(公告)号：US4992374A

公开(公告)日：1991-02-12

申请号：US79680

申请日：1987-07-30

申请人： Masanobu Sugimoto ,  Fukumi Nishimaki ,  Tadashi Maruyama ,  Keizaburo Miki ,  Michio Morita ,  Kazuyoshi Suzuki

发明人： Masanobu Sugimoto ,  Fukumi Nishimaki ,  Tadashi Maruyama ,  Keizaburo Miki ,  Michio Morita ,  Kazuyoshi Suzuki

IPC分类号： C12N15/09 ,  A61K39/00 ,  A61K39/285 ,  C12N7/00 ,  C12N7/06 ,  C12N15/00 ,  C12N15/863

CPC分类号： C12N15/86 ,  C12N15/00 ,  C12N7/00 ,  C12N2710/24121 ,  C12N2710/24143 ,  C12N2710/24162

摘要： An improved mutant vaccinia virus providing a pock and plaque size on RK13 cells that is approximately the same as those of the Lister original, having a proliferation potency on YTV cells that is approximately the same as that of the Lister original, and having a neurovirulence, assessed by a recovery of an intrabrain virus, that is lower than that of the Lister original; and a process for the production thereof.

公开(公告)号：US4930105A

公开(公告)日：1990-05-29

申请号：US178609

申请日：1988-04-07

申请人： Osamu Matsumoto ,  Tadashi Maruyama ,  Hiroyoshi Murata ,  Isao Abe ,  Tomohisa Shigematsu ,  Kazuyoshi Shinada ,  Yasoji Suzuki ,  Ichiro Kobayashi

发明人： Osamu Matsumoto ,  Tadashi Maruyama ,  Hiroyoshi Murata ,  Isao Abe ,  Tomohisa Shigematsu ,  Kazuyoshi Shinada ,  Yasoji Suzuki ,  Ichiro Kobayashi

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/0425

摘要： A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.

公开(公告)号：US20130196404A1

公开(公告)日：2013-08-01

申请号：US13359797

申请日：2012-01-27

申请人： Sumihiro Koyama ,  Tadashi Maruyama ,  Chiaki Kato ,  Yuichi Nogi ,  Yuji Hatada ,  Yukari Ohta ,  Masaaki Konishi ,  Taishi Tsubouchi

发明人： Sumihiro Koyama ,  Tadashi Maruyama ,  Chiaki Kato ,  Yuichi Nogi ,  Yuji Hatada ,  Yukari Ohta ,  Masaaki Konishi ,  Taishi Tsubouchi

IPC分类号： C12N13/00

CPC分类号： C12N13/00 ,  C12N11/14

摘要： A method for immobilizing living microorganisms includes a step (1) of disposing a solution containing microorganisms as an electrolyte on the surface of a substrate at least one portion of which is an electrode, and applying a constant potential to the electrode to cause at least a portion of the microorganisms to attach to the surface of the substrate. The constant potential in step (1) is greater than −0.5 V but not greater than −0.2 V (vs Ag/AgCl) or greater than +0.2 V but not greater than +0.4 V (vs Ag/AgCl). The electrolyte in step (1) does not contain a source of nutrition for the microorganisms.

摘要翻译： 固定活体微生物的方法包括将含有微生物作为电解质的溶液设置在基材的表面上的步骤（1），其中至少一部分是电极，并向电极施加恒定电位，使至少 部分微生物附着到基底表面。 步骤（1）中的恒定电位大于-0.5V但不大于-0.2V（相对于Ag / AgCl）或大于+ 0.2V但不大于+0.4V（相对于Ag / AgCl）。 步骤（1）中的电解质不含微生物的营养来源。

公开(公告)号：US5058062A

公开(公告)日：1991-10-15

申请号：US431845

申请日：1989-11-06

申请人： Yukio Wada ,  Tadashi Maruyama ,  Toshimasa Nakamura

发明人： Yukio Wada ,  Tadashi Maruyama ,  Toshimasa Nakamura

IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C16/28 ,  G11C7/065

摘要： A nonvolatile memory device has a memory cell having its gate connected to a word line, its source connected to a ground potential and its drain connected to a power supply voltage via a bit line and a dummy cell having its gate connected to the word line, its source connected to the source potential and its drain connected to the power supply voltage via a dummy bit line. The bit line and the dummy bit line are connected to reset and set terminals of a sense amplifier circuit comprising a flip-flop circuit and a latch type of sense amplifier. The conductance of the dummy cell is made smaller than that of the memory cell so that the speed at which the potential on the bit line is lowered depends on the state of injection of electrons into the memory cell as compared with the speed at which the potential on the dummy bit line at a time of reading data. The flip-flop circuit is reset or set in accordance with the speed at which the potential on the bit line is lowered and then the latch type of sense amplifier operates to latch the output of the flip-flop circuit and output it as read data.

公开(公告)号：US4970409A

公开(公告)日：1990-11-13

申请号：US332325

申请日：1989-04-03

申请人： Yukio Wada ,  Tadashi Maruyama

发明人： Yukio Wada ,  Tadashi Maruyama

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07 ,  H03K17/06 ,  H03K19/017

CPC分类号： G11C5/145 ,  H03K17/063 ,  H03K19/01742

摘要： A voltage multiplier for a use in a non-volatile semiconductor memory and operated at a low operation voltage with a reduced area comprising a plurality of cascade-connected basic circuits.

摘要翻译： 一种在非易失性半导体存储器中使用的电压倍增器，并且在具有包括多个级联连接的基本电路的减小区域的低工作电压下操作。