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公开(公告)号：US5815103A
公开(公告)日：1998-09-29
申请号：US634306
申请日：1996-04-16
CPC分类号： H03M1/745
摘要： A digital-to-analog converter that includes pairs of positive and negative current sources that are connected through switches to two differential output lines. The switches are controlled as a function of a digital data. Each pair of current sources includes a pair of transistors of an output stage of a transconductance amplifier. The transconductance amplifier receives a reference voltage at a non-inverting input, and receives at an inverting input, the voltage at the middle node of a bridge of resistors that is connected between the two differential out-put lines. The output of the converter is the voltage between the two differential output lines.
摘要翻译： 一个数模转换器，包括通过开关连接到两个差分输出线的正和负电流源对。 开关作为数字数据的功能进行控制。 每对电流源包括跨导放大器的输出级的一对晶体管。 跨导放大器在非反相输入端接收参考电压，并在反相输入端接收连接在两个差分输出线之间的电阻桥的中间节点处的电压。 转换器的输出是两个差分输出线之间的电压。
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2.发明授权
公开(公告)号：US5696510A
公开(公告)日：1997-12-09
申请号：US443517
申请日：1995-05-18
CPC分类号： H03M1/1215 , H03M1/148 , H03M1/365
摘要： The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.
摘要翻译： 本公开是半闪存型的模数转换器，其提供两个模拟输入信号的复用，因此仅需要一个转换器模块。 它包括用于确定转换信号的最高有效位的粗略比较器块，并且还确定确定转换信号的最低有效位的两个精细比较器块的电压范围，其中每个输入信号被连接到一个精细 比较器块和所述粗略比较器块将第一和第二输入信号与参考电压进行比较。 模拟 - 数字转换器可以有利地用于处理电视信号。
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公开(公告)号：US6125094A
公开(公告)日：2000-09-26
申请号：US66726
申请日：1998-04-23
摘要： A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.
摘要翻译： 电流放大器包括用于固定放大器的输入端的电压的共源共栅晶体管; 连接在所述输入端和第一电源电压之间的第一恒流源; 第二恒流源，用于提供连接在第二电源电压和共源共栅晶体管之间的低于第一电流源的电流; 第二晶体管，其不同于共源共栅晶体管的类型，连接在输入和第二电源电压之间，并由共源共栅晶体管和第二电流源之间的节点控制; 以及与第二晶体管相同类型的输出晶体管，连接到第二电源电压并由节点控制。
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公开(公告)号：US5867066A
公开(公告)日：1999-02-02
申请号：US631733
申请日：1996-04-11
摘要： A current amplifier includes a cascode transistor for fixing the voltage of an input of the amplifier; a first constant current source connected between the input and a first supply voltage; a second constant current source, for providing a current lower than the first current source, connected between a second supply voltage and the cascode transistor; a second transistor, of different type than the cascode transistor, connected between the input and the second supply voltage, and controlled by the node between the cascode transistor and the second current source; and an output transistor of same type as the second transistor, connected to the second supply voltage and controlled by the node.
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5.发明授权Method of enhancing the noise immunity of a phase-locked loop, and device implementing this method 失效提高锁相环噪声抗扰度的方法，以及实现该方法的装置
公开(公告)号：US5663688A
公开(公告)日：1997-09-02
申请号：US553376
申请日：1996-04-02
CPC分类号： H04N5/126 , H03L7/085 , H03L7/14 , H03L7/191 , H03L7/0891
摘要： The present invention relates to a method of enhancing the noise Immunity of a phase-locked loop. The phase-locked loop includes a comparator and apparatus for inhibiting the action of the comparator on the phase-locked loop. According to the method, the inhibition is lifted during a main time window resulting from the intersection of a first time window derived from the input signal of the phase-locked loop, and of a second time window derived from the loop-return signal.
摘要翻译： PCT No.PCT / FR94 / 00659 Sec。 371日期：1996年4月2日 102（e）日期1996年4月2日PCT提交1994年6月3日PCT公布。 WO94 / 29964 PCT公开号 日期1994年12月22日本发明涉及增强锁相环噪声抗扰度的方法。 锁相环包括用于抑制比较器在锁相环上的动作的比较器和装置。 根据该方法，在由从锁相环的输入信号导出的第一时间窗口与从循环返回信号导出的第二时间窗口的交点产生的主时间窗口期间，禁止被提升。
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公开(公告)号：US07215723B2
公开(公告)日：2007-05-08
申请号：US10239291
申请日：2001-03-20
申请人： Pierre Rizzo , Francis Dell'Ova
发明人： Pierre Rizzo , Francis Dell'Ova
IPC分类号： H04L27/00
CPC分类号： G06K19/0701 , G06K7/0008 , G06K19/0723 , H03D1/10 , H03K5/082 , H04L25/061
摘要： The invention concerns a demodulator of an amplitude-modulated signal (Vdb), characterised in that it comprises a peak detecting cell (DCR) capable of extracting the reference modulating signal (Vpeak1) of the modulated signal (Vdb); a first demodulator (FE) adapted to detect the peak of the reference modulating signal (Vpeak1) to generate a high comparison threshold and locate the start of the modulation, a second demodulator (RE) adapted to detect a trough of the reference modulating signal (Vpeak1) to generate a low comparison threshold and locate the end of the modulation; a logic processing unit capable of supplying the demodulated signal (Vdemod).
摘要翻译： 本发明涉及一种幅度调制信号（Vdb）的解调器，其特征在于它包括能够提取调制信号（Vdb）的参考调制信号（Vpeak 1）的峰值检测单元（DCR）; 适于检测参考调制信号（Vpeak 1）的峰值以产生高比较阈值并定位调制开始的第一解调器（FE），适于检测参考调制信号的谷值的第二解调器（RE） （Vpeak 1）产生低比较阈值并定位调制结束; 能够提供解调信号（Vdemod）的逻辑处理单元。
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7.发明授权Method for adjusting an electrical parameter on an integrated electronic component 有权用于调整集成电子部件上的电参数的方法公开(公告)号：US07704757B2
公开(公告)日：2010-04-27
申请号：US10276509
申请日：2001-03-13
申请人： Francis Dell'Ova , Frank Lhermet , Dominique Poirot , Stephane Rayon , Bertrand Gomez , Nicole Lessoile , Pierre Rizzo
发明人： Francis Dell'Ova , Frank Lhermet , Dominique Poirot , Stephane Rayon , Bertrand Gomez , Nicole Lessoile , Pierre Rizzo
CPC分类号： H01L22/14 , H01L22/20 , H01L23/66 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for manufacturing an integrated electronic component arranged on a substrate wafer. According to the method, at least one metallization step is performed, and a value of an electrical parameter of the integrated electronic component is determined after the at least one metallization step. A subsequent metallization step is performed after determining the value of the electrical parameter. The subsequent metallization step is performed using an adjustment mask chosen from n predefined masks based on a desired value of the electrical parameter, so as to obtain the desired value of the electrical parameter of the integrated electronic component after manufacturing. In one preferred embodiment, a series of electrical tests is performed on the wafer using test equipment, and the value of the electrical parameter is determined using the same test equipment as is used to perform the series of electrical tests.
摘要翻译： 提供一种用于制造布置在基板晶片上的集成电子部件的方法。 根据该方法，执行至少一个金属化步骤，并且在至少一个金属化步骤之后确定集成电子部件的电参数的值。 在确定电参数的值之后执行随后的金属化步骤。 随后的金属化步骤使用基于电参数的期望值从n个预定义掩模中选择的调整掩模来执行，以便在制造之后获得集成电子部件的电参数的期望值。 在一个优选实施例中，使用测试设备对晶片进行一系列电测试，并且使用与用于执行一系列电测试的相同的测试设备来确定电参数的值。
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公开(公告)号：US5574407A
公开(公告)日：1996-11-12
申请号：US532647
申请日：1995-09-28
CPC分类号： H03L7/14 , H03L7/0991 , H03L7/113 , H04N7/122 , H03B2201/02 , H03B2201/0266 , H03J2200/10 , Y10S331/02
摘要： A phase detector of a phase-lock-loop circuit measures a phase error between an output signal of an oscillator and a synchronizing signal. When a difference between the phase error that is measured in a pair of horizontal line periods exceeds a first magnitude, that is indicative of phase error inconsistency, the phase of the oscillator output signal is not corrected and the phase-lock-loop circuit operates in an idle mode of operation.
摘要翻译： PCT No.PCT / US94 / 04291 Sec。 371 1995年9月28日第 102（e）1995年9月28日PCT PCT 1994年4月19日PCT公布。 公开号WO94 / 24768 日期1994年10月27日锁相环电路的相位检测器测量振荡器的输出信号与同步信号之间的相位误差。 当在一对水平行周期内测量的相位误差之间的差异超过第一幅度，表示相位误差不一致时，振荡器输出信号的相位不被校正，并且锁相环电路在 空闲操作模式。
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9.发明授权公开(公告)号：US07975921B2
公开(公告)日：2011-07-12
申请号：US12103570
申请日：2008-04-15
申请人： Christophe Mani , Francis Dell'Ova , Pierre Rizzo
发明人： Christophe Mani , Francis Dell'Ova , Pierre Rizzo
IPC分类号： G06K7/06
CPC分类号： H04B5/0056 , G06K7/0008 , G06K19/0723
摘要： An inductive coupling reader includes a passive interface circuit for modulating the impedance of an antenna circuit and extracting from the antenna circuit a data signal and a RF clock signal, and circuitry for coupling the reader to a removable security module. The reader includes an emulation circuit for opening a RF transmission channel with another reader, a non-removable electrical link linking the emulation circuit to the passive interface circuit, by which the data signal and the RF clock signal are supplied to the emulation circuit, and a data bus clocked by a bus clock signal having a frequency inferior to the frequency of the RF clock signal, for linking the emulation circuit to the removable security module. The reader has low electrical consumption.
摘要翻译： 电感耦合读取器包括用于调制天线电路的阻抗并从天线电路提取数据信号和RF时钟信号的无源接口电路，以及用于将读取器耦合到可拆卸安全模块的电路。 读取器包括用于与另一个读取器打开RF传输通道的仿真电路，将仿真电路连接到无源接口电路的不可拆卸电气连接，通过该无源接口电路将数据信号和RF时钟信号提供给仿真电路，以及 由总线时钟信号计时的数据总线，其频率低于RF时钟信号的频率，用于将仿真电路链接到可移除的安全模块。 读卡器电耗低。
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10.发明申请公开(公告)号：US20090101716A1
公开(公告)日：2009-04-23
申请号：US12103570
申请日：2008-04-15
申请人： Christophe Mani , Francis Dell'Ova , Pierre Rizzo
发明人： Christophe Mani , Francis Dell'Ova , Pierre Rizzo
IPC分类号： G06K7/06
CPC分类号： H04B5/0056 , G06K7/0008 , G06K19/0723
摘要： An inductive coupling reader includes a passive interface circuit for modulating the impedance of an antenna circuit and extracting from the antenna circuit a data signal and a RF clock signal, and circuitry for coupling the reader to a removable security module. The reader includes an emulation circuit for opening a RF transmission channel with another reader, a non-removable electrical link linking the emulation circuit to the passive interface circuit, by which the data signal and the RF clock signal are supplied to the emulation circuit, and a data bus clocked by a bus clock signal having a frequency inferior to the frequency of the RF clock signal, for linking the emulation circuit to the removable security module. The reader has low electrical consumption.
摘要翻译： 电感耦合读取器包括用于调制天线电路的阻抗并从天线电路提取数据信号和RF时钟信号的无源接口电路，以及用于将读取器耦合到可拆卸安全模块的电路。 读取器包括用于与另一个读取器打开RF传输通道的仿真电路，将仿真电路连接到无源接口电路的不可拆卸电气连接，通过该无源接口电路将数据信号和RF时钟信号提供给仿真电路，以及 由总线时钟信号计时的数据总线，其频率低于RF时钟信号的频率，用于将仿真电路链接到可移除的安全模块。 读卡器电耗低。
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