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    Lapping machine
    2.
    发明授权
    Lapping machine 失效
    研磨机

    公开(公告)号：US06511365B2

    公开(公告)日：2003-01-28

    申请号：US09459036

    申请日：1999-12-10

    申请人： Shigeo Terashima ,  Hiroyuki Miyazawa

    发明人： Shigeo Terashima ,  Hiroyuki Miyazawa

    IPC分类号： B24B100

    CPC分类号： B24B53/017 ,  B24B37/048 ,  B24B49/14 ,  G11B5/1871 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/3903

    摘要： An object of the present invention is to provide a lapping machine in which abrasive grains can be efficiently and completely removed from a lapping plate. In the lapping machine of the present invention, a lapping plate has a lapping face and rotates about a rotary shaft. A moving member has a wiping face extended in a longitudinal and moves, in a plane parallel to the lapping face of the lapping plate, in the direction perpendicular to the wiping face. A driving mechanism moves the moving member. With this structure, the moving member securely catches and removes foreign substances from the lapping plate. The foreign substances left can be completely removed in a short time and the working efficiency of the lapping steps can be highly improved.

    摘要翻译： 本发明的目的是提供一种研磨机，其中磨粒可以从研磨盘中有效地和完全地除去。 在本发明的研磨机中，研磨板具有研磨面并围绕旋转轴旋转。 移动构件具有沿纵向延伸的擦拭面，在与研磨板的研磨面平行的平面中，在与擦拭面垂直的方向上移动。 驱动机构移动移动构件。 利用这种结构，移动构件牢固地捕获并从研磨板上去除异物。 留下的异物可以在短时间内完全去除，研磨步骤的工作效率可以大大提高。

    Base body of reflecting mirror and method for preparing the same
    3.
    发明授权
    Base body of reflecting mirror and method for preparing the same 失效
    反射镜的基体及其制备方法

    公开(公告)号：US5640282A

    公开(公告)日：1997-06-17

    申请号：US775095

    申请日：1991-10-11

    申请人： Yoshiaki Ise ,  Hiroyuki Miyazawa ,  Hiroyuki Kimura ,  Shinichi Okoshi ,  Tatsumasa Nakamura ,  Toshiyuki Kato

    发明人： Yoshiaki Ise ,  Hiroyuki Miyazawa ,  Hiroyuki Kimura ,  Shinichi Okoshi ,  Tatsumasa Nakamura ,  Toshiyuki Kato

    IPC分类号： G02B5/08 ,  G02B5/10 ,  G02B7/182 ,  G02B7/183

    CPC分类号： G02B7/183 ,  G02B5/08 ,  G02B5/10 ,  Y10S359/90 ,  Y10T428/249969 ,  Y10T428/249976 ,  Y10T428/249977

    摘要： A light-weight base body of a reflecting mirror, such as those used in reflecting astronomical telescopes, is proposed which is made from fused silica glass or high-silica glass and is advantageous in respect of the excellent thermal and mechanical stability in dimensions to ensure high performance of the reflecting mirror. The base body is composed of a front plate, i.e. a surface plate to provide the optical surface, and a supporting body of porous foamed glass integrally bonded to the front plate. These two parts of the base body can be bonded together by sandwiching a layer of a finely divided silica powder therebetween and heating the assemblage at a temperature higher than the softening point of the silica powder so that the silica powder is softened or melted to firmly join the two parts sandwiching the powder layer. The base body can be further improved in respect of the mechanical stability by providing a rear plate backing the porous foamed body and a reinforcing hoop-like side layer surrounding the side surface of the porous foamed body, each made from fused quartz glass or high-silica glass and bonded to the porous foamed body by utilizing melting of a layer of silica powder therebetween.

    摘要翻译： 提出了一种反射镜的轻质基体，例如用于反射天文望远镜的反射镜，其由熔融石英玻璃或高硅石玻璃制成，并且在尺寸方面优良的热和机械稳定性是有利的，以确保 高性能的反光镜。 基体由前板，即提供光学表面的表面板和与前板一体地结合的多孔泡沫玻璃的支撑体组成。 基体的这两个部分可以通过在其间夹有细碎的二氧化硅粉末层而将它们粘合在一起，并在高于二氧化硅粉末的软化点的温度下加热组合物，使得二氧化硅粉末软化或熔化以牢固地连接 两部分夹在粉末层上。 通过提供背面多孔泡沫体的后板和围绕多孔泡沫体的侧表面的加强箍型侧层，每个由熔融石英玻璃或高熔点石英玻璃制成，可以进一步改善基体的机械稳定性， 二氧化硅玻璃，并通过利用二氧化硅粉末之间的熔融而与多孔发泡体结合。

    Method of producing a semiconductor memory device having trench capacitors
    7.
    发明授权
    Method of producing a semiconductor memory device having trench capacitors 失效
    制造具有沟槽电容器的半导体存储器件的方法

    公开(公告)号：US4921815A

    公开(公告)日：1990-05-01

    申请号：US203931

    申请日：1988-06-08

    申请人： Hiroyuki Miyazawa

    发明人： Hiroyuki Miyazawa

    IPC分类号： H01L27/10 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

    CPC分类号： H01L27/10829

    摘要： A D-RAM is disclosed which isolates the capacitors of memory cells and also isolates the adjacent memory cells by utilizing trenches formed on a semiconductor substrate. The device is particularly intended to the area of each memory cell and prevent the occurrence of a leakage current between the adjacent memory cells. Two side walls of the trench are used as the capacitors of two different memory cells, respectively, and these capacitors are isolated from each other by a thick oxide film that is formed on the bottom of each trench.

    摘要翻译： 公开了一种D-RAM，其隔离存储单元的电容器，并且还通过利用形成在半导体衬底上的沟槽来隔离相邻的存储单元。 该器件特别用于每个存储单元的区域，并且防止相邻存储单元之间发生漏电流。 沟槽的两个侧壁分别用作两个不同存储单元的电容器，并且这些电容器通过形成在每个沟槽的底部上的厚氧化膜彼此隔离。

    Method of making a semiconductor memory circuit device
    9.
    发明授权
    Method of making a semiconductor memory circuit device 失效
    制造半导体存储器电路器件的方法

    公开(公告)号：US5389558A

    公开(公告)日：1995-02-14

    申请号：US104014

    申请日：1993-08-10

    申请人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    发明人： Naokatsu Suwanai ,  Hiroyuki Miyazawa ,  Atushi Ogishima ,  Masaki Nagao ,  Kyoichiro Asayama ,  Hiroyuki Uchiyama ,  Yoshiyuki Kaneko ,  Takashi Yoneoka ,  Kozo Watanabe ,  Kazuya Endo ,  Hiroki Soeda

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10844 ,  H01L27/10805 ,  H01L27/10808

    摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.

    摘要翻译： 在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有 栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

    Semiconductor integrated circuit device including a dielectric breakdown prevention circuit
    10.
    发明授权
    Semiconductor integrated circuit device including a dielectric breakdown prevention circuit 失效
    包括绝缘击穿防止电路的半导体集成电路装置

    公开(公告)号：US5268587A

    公开(公告)日：1993-12-07

    申请号：US786750

    申请日：1991-11-01

    申请人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

    发明人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

    IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78

    CPC分类号： H01L27/10805 ,  H01L27/105

    摘要： A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.

    摘要翻译： 半导体集成电路器件包括耦合到外部端子的绝缘击穿防止电路，用于保护输入级电路。 防止电路具有双极晶体管和互补MISFET，其包括第一导电类型的第一MISFET和第二导电类型的第二MISFET。 第一导电类型的第一半导体区域由与其中形成第二MISFET的阱区相同的层形成。 第二导电类型的第二半导体区域通过与第二MISFET的源极和漏极区域相同的层在所述第一半导体区域中形成。 这些第一和第二半导体区域形成第一PN结二极管。 外部端子电耦合到所述第二半导体区域的一个端部。 高杂质导电型掩埋的第三半导体区域位于所述第二半导体区域的下方，并且由与隔离双极晶体管的区域相同的层形成。 该第三区域设置在所述第一半导体区域的底表面。 第二导电类型的第四半导体区域也通过与用于双极晶体管的集电极接触区域的相同的层形成在所述第一半导体区域中，并且与所述第二半导体区域的与第三半导体接触的另一个端部连接 地区。 第四半导体区域耦合到输入级电路，并且第三和第四半导体区域形成第二PN结二极管。