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    Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate
    1.
    发明授权
    Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate 有权
    晶体管结构，存储单元，DRAM以及在半导体衬底中制造晶体管结构的方法

    公开(公告)号：US07183156B2

    公开(公告)日：2007-02-27

    申请号：US10975085

    申请日：2004-10-28

    申请人： Matthias Goldbach ,  Ulrich Frey ,  Björn Fischer

    发明人： Matthias Goldbach ,  Ulrich Frey ,  Björn Fischer

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10888 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/42368

    摘要： Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

    摘要翻译： 晶体管结构，具有连接到待绝缘的电荷存储装置的一个源极/漏极区域包括非对称栅极导体结构。 在面向一个源极/漏极区域的第一侧壁处，不对称栅极导体结构具有较大厚度的侧壁氧化物和具有比相对的第二侧壁长的长度的鸟嘴结构。 对于栅极导体结构的相同特征尺寸，有效沟道长度增加。 可以以更高的密度实现存储单元。

    Semiconductor device and corresponding fabrication method
    2.
    发明授权
    Semiconductor device and corresponding fabrication method 失效
    半导体器件及相应的制造方法

    公开(公告)号：US07045855B2

    公开(公告)日：2006-05-16

    申请号：US10777207

    申请日：2004-02-13

    申请人： Björn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlösser

    发明人： Björn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlösser

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/31612 ,  H01L21/31616 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/56 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/785

    摘要： A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

    摘要翻译： 具有栅极结构的半导体器件，所述栅极结构具有由第一材料制成的第一栅极电介质，所述第一材料具有位于所述沟道区域正上方的第一厚度和第一介电常数，以及由第二栅极电介质构成的覆盖的第二栅极电介质 材料具有明显大于第一介电常数的第二厚度和第二介电常数; 并且第一栅极电介质的第一厚度和第二栅极电介质的第二厚度被选择为使得具有第一栅极电介质的栅极结构的相应厚度以获得相同的阈值电压至少与 厚度等于第一厚度和第二厚度之和的厚度。 本发明还涉及相应的制造方法。

    Fabrication method for a semiconductor structure and corresponding semiconductor structure
    3.
    发明申请
    Fabrication method for a semiconductor structure and corresponding semiconductor structure 有权
    半导体结构的制造方法和相应的半导体结构

    公开(公告)号：US20050173729A1

    公开(公告)日：2005-08-11

    申请号：US11035705

    申请日：2005-01-14

    申请人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

    发明人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L27/085 ,  H01L27/105 ,  H01L29/49 ,  H01L29/739 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

    CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/6656

    摘要： The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps: provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).

    摘要翻译： 本发明提供一种用于半导体结构和相应的半导体结构的制造方法。 制造方法包括以下步骤：提供具有栅极电介质（5）的半导体衬底（1）; 提供多个多层细长的栅极叠层（GS1; GS2），其基本上在栅极电介质（5）上彼此平行地延伸，该栅极堆叠具有由硅制成的最底层（10）; 提供由栅极叠层（GS1; GS2）和栅极电介质（5）制成的由第一材料制成的第一衬垫层（60）未被覆盖在其后面，衬垫层的厚度（h）小于 由硅制成的最下层（10）的厚度（h'）; 在第一衬垫层（60）上设置由栅极堆叠（GS1; GS2）的垂直侧壁上的由第二材料制成的侧壁间隔物（70），第一衬里层（60）的位于栅极电介质 （5）在栅极堆栈（GS 1; GS 2）之间保持自由; 为了横向露出由栅极堆叠（GS1; GS2）的硅制成的最底层（10）的目的，相对于侧壁间隔物（70）选择性地去除第一衬里层（60） 以及为了在栅极堆叠（GS1; GS2）上形成侧壁氧化物区域（50'），未覆盖的最底层（10）的选择性氧化。

    Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate
    4.
    发明申请
    Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate 有权
    晶体管结构，存储单元，DRAM以及在半导体衬底中制造晶体管结构的方法

    公开(公告)号：US20050116293A1

    公开(公告)日：2005-06-02

    申请号：US10975085

    申请日：2004-10-28

    申请人： Matthias Goldbach ,  Ulrich Frey ,  Bjorn Fischer

    发明人： Matthias Goldbach ,  Ulrich Frey ,  Bjorn Fischer

    IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L29/423 ,  H01L27/01

    CPC分类号： H01L27/10888 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/10873 ,  H01L29/42368

    摘要： Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

    摘要翻译： 晶体管结构，具有连接到待绝缘的电荷存储装置的一个源极/漏极区域包括非对称栅极导体结构。 在面向一个源极/漏极区域的第一侧壁处，不对称栅极导体结构具有较大厚度的侧壁氧化物和具有比相对的第二侧壁长的长度的鸟嘴结构。 对于栅极导体结构的相同特征尺寸，有效沟道长度增加。 可以以更高的密度实现存储单元。

    Fabrication method for a semiconductor structure and corresponding semiconductor structure
    5.
    发明授权
    Fabrication method for a semiconductor structure and corresponding semiconductor structure 有权
    半导体结构的制造方法和相应的半导体结构

    公开(公告)号：US07235447B2

    公开(公告)日：2007-06-26

    申请号：US11035705

    申请日：2005-01-14

    申请人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

    发明人： Ulrich Frey ,  Matthias Goldbach ,  Dirk Offenberg

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L21/823468 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/6656

    摘要： The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure. The fabrication method comprises the following steps:provision of a semiconductor substrate (1) with a gate dielectric (5); provision of a plurality of multilayered, elongate gate stacks (GS1; GS2) which essentially run parallel to one another on the gate dielectric (5), which gate stacks have a bottommost layer (10) made of silicon; provision of a first liner layer (60) made of a first material over the gate stacks (GS1; GS2) and the gate dielectric (5) uncovered beside the latter, the thickness (h) of which liner layer is less than a thickness (h′) of the bottommost layer (10) made of silicon; provision of sidewall spacers (70) made of a second material on the vertical sidewalls of the gate stacks (GS1; GS2) over the first liner layer (60), a region of the first liner layer (60) over the gate dielectric (5) between the gate stacks (GS1; GS2) remaining free; selective removal of the first liner layer (60) with respect to the sidewall spacers (70) for the purpose of laterally uncovering the bottommost layer (10) made of silicon of the gate stacks (GS1; GS2); and selective oxidation of the uncovered bottommost layer (10) for the purpose of forming sidewall oxide regions (50′) on the gate stacks (GS1; GS2).

    摘要翻译： 本发明提供一种用于半导体结构和相应的半导体结构的制造方法。 制造方法包括以下步骤：提供具有栅极电介质（5）的半导体衬底（1）; 提供多个多层细长的栅极叠层（GS1; GS2），其基本上在栅极电介质（5）上彼此平行地延伸，该栅极堆叠具有由硅制成的最底层（10）; 提供由栅极叠层（GS1; GS2）和栅极电介质（5）制成的由第一材料制成的第一衬垫层（60）未被覆盖在其后面，衬垫层的厚度（h）小于 由硅制成的最下层（10）的厚度（h'）; 在第一衬垫层（60）上设置由栅极堆叠（GS1; GS2）的垂直侧壁上的由第二材料制成的侧壁间隔物（70），第一衬里层（60）的位于栅极电介质 （5）在栅极堆栈（GS 1; GS 2）之间保持自由; 为了横向露出由栅极堆叠（GS1; GS2）的硅制成的最底层（10）的目的，相对于侧壁间隔物（70）选择性地去除第一衬里层（60） 以及为了在栅极堆叠（GS1; GS2）上形成侧壁氧化物区域（50'），未覆盖的最底层（10）的选择性氧化。

    Method of removing refractory metal layers and of siliciding contact areas
    7.
    发明授权
    Method of removing refractory metal layers and of siliciding contact areas 失效
    去除难熔金属层和硅化接触区域的方法

    公开(公告)号：US07679149B2

    公开(公告)日：2010-03-16

    申请号：US11669500

    申请日：2007-01-31

    申请人： Audrey Beckert ,  Matthias Goldbach ,  Clemens Fitz

    发明人： Audrey Beckert ,  Matthias Goldbach ,  Clemens Fitz

    IPC分类号： H01L29/76

    CPC分类号： H01L21/28518 ,  H01L21/32134 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/66545 ,  H01L29/78

    摘要： A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.

    摘要翻译： 公开了一种与硅化钴形成接触的方法。 例如，在用SOM溶液硅化后，例如包括例如作为硅化的初始层的钴的钴的沉积层的未反应部分和包括钛并通过阴极射线溅射沉积的氧化保护层可以是 相对于硅化钴和其它致密的金属结构和金属层，快速且高选择性地去除。

    Method for fabricating a memory cell
    9.
    发明授权
    Method for fabricating a memory cell 失效
    用于制造存储单元的方法

    公开(公告)号：US07192830B2

    公开(公告)日：2007-03-20

    申请号：US10862818

    申请日：2004-06-07

    申请人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

    发明人： Matthias Goldbach ,  Thomas Mikolajick ,  Albert Birner

    IPC分类号： H01L21/336

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7887

    摘要： Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

    摘要翻译： 将硅纳米晶体作为存储层（6）施加，并且使用间隔元件（11）相对于栅电极（5）横向去除。 通过掺杂剂的注入，源极/漏极区域（2）以相对于存储层（6）的自对准方式制造。 存储层（6）的部分被栅极（5）和栅极电介质（4）中断，使得沟道区域（3）的中心部分不被存储层（6）覆盖。 该存储单元适合作为虚拟地面架构中的多位闪存单元。

    Memory and method for fabricating it
    10.
    发明申请
    Memory and method for fabricating it 审中-公开
    记忆及其制作方法

    公开(公告)号：US20060275981A1

    公开(公告)日：2006-12-07

    申请号：US11442602

    申请日：2006-05-30

    申请人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

    发明人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10867

    摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

    摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。