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1.发明申请Apparatus and method for modeling queueing systems with highly variable traffic arrival rates 失效用于建模具有高可变流量到达率的排队系统的装置和方法公开(公告)号：US20050122987A1
公开(公告)日：2005-06-09
申请号：US10731862
申请日：2003-12-09
申请人： Michael Ignatowski , Noshir Wadia
发明人： Michael Ignatowski , Noshir Wadia
CPC分类号： H04L41/145 , H04L43/0852 , H04L49/90
摘要： An apparatus and method are provided for modeling queuing systems with highly variable traffic arrival rates. The apparatus and method include a means to associate a value with a pattern of highly variable arrival rates that is simple and intuitive, and a means to accurately model queuing delays in systems that are characterized by bursts of arrival activity. The queuing delay is determined by a sum of queuing delays after first applying a weighting factor to the queuing delay based upon a random arrival rate, and a different weighting factor to the queuing delay based upon a bursty variable arrival rate. The weighting factors are variants of the server utilization. The model facilitates specification of server characteristics and configurations to meet response time metrics.
摘要翻译： 提供了一种用于对具有高度可变的交通量到达率的排队系统进行建模的装置和方法。 装置和方法包括将值与简单和直观的高度可变到达速率的模式相关联的手段，以及用于在以突发的到达活动为特征的系统中精确地建模排队延迟的手段。 基于随机到达速率首先将加权因子应用于排队延迟，以及基于突发可变到达速率的排队延迟的不同加权因子，排队延迟由排队延迟的和确定。 加权因子是服务器利用率的变体。 该模型有助于规范服务器特性和配置以满足响应时间度量。
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公开(公告)号：US09135185B2
公开(公告)日：2015-09-15
申请号：US13726143
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译： 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。
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3.发明授权Method and apparatus for controlling state information retention in an apparatus 有权用于控制装置中的状态信息保持的方法和装置公开(公告)号：US08879301B2
公开(公告)日：2014-11-04
申请号：US13616142
申请日：2012-09-14
申请人： David Mayhew , Mark Hummel , Michael Ignatowski
发明人： David Mayhew , Mark Hummel , Michael Ignatowski
CPC分类号： G11C13/0002 , G11C5/005 , G11C11/4125 , G11C14/0045 , H03K19/0016 , H03K19/0019
摘要： A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.
摘要翻译： 用于控制状态信息保持的方法和装置至少确定集成电路中至少一个处理电路（例如一个或多个CPU或GPU核心或管线）的状态信息保存或恢复条件。 响应于确定状态信息保存或恢复条件，该方法和装置控制将处理电路上运行的不同虚拟机的状态信息的保存或恢复中的任一个或两者转换为相应的裸片上持续的可变电阻存储器。 状态信息保存或恢复条件是虚拟机级状态信息保存或恢复条件。 每个不同虚拟机的状态信息由在每个虚拟机基础上分配的不同的片上可变电阻存储器单元进行保存或恢复。
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4.发明授权Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作公开(公告)号：US08122216B2
公开(公告)日：2012-02-21
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译： 提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。 特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。
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公开(公告)号：US07099816B2
公开(公告)日：2006-08-29
申请号：US10174030
申请日：2002-06-17
申请人： Michael Ignatowski , Noshir Cavas Wadia , Peng Ye
发明人： Michael Ignatowski , Noshir Cavas Wadia , Peng Ye
CPC分类号： G06Q10/04 , G06F11/3419 , G06F11/3447
摘要： The present invention discloses a method, system and article of manufacture for performing analytic modeling on a computer system by handling a plurality of predefined system criteria directed to a modeled computer system. The present invention provides means for the user of an analytic model to specify (i.e. enable) any number of predefined system criteria that must all be simultaneously satisfied. The modeling methodology uses a variation of the well-known Mean Value Analysis technique in its calculations. Response times, resource utilizations, and resource queue lengths are initially estimated for a small user arrival rate. An iterative method is used to gradually increase the user arrival rate by a constant value. For each iteration, response times, resource utilizations, and resource queue lengths are calculated. Then for all the criteria, which have been enabled, it is checked to see if the value limits specified for those criteria have exceeded. If not, the model calculation results are saved and next iteration is started. The model iterations continue with a gradually increasing user arrival rate until one or more of the modeling criteria are exceeded. At that time the model outputs the results from the previous iteration (i.e. the saved results where all the criteria were still satisfied), and the modeling calculations are finished. The model results may be used as input for further processing.
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6.发明申请Method, system, and computer program product for dynamically managing power in microprocessor chips according to present processing demands 有权方法，系统和计算机程序产品，用于根据当前的处理需求动态管理微处理器芯片的电源公开(公告)号：US20050283679A1
公开(公告)日：2005-12-22
申请号：US10860407
申请日：2004-06-03
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译： 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别执行该过程所需的硬件元素。 微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。
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公开(公告)号：US20130159812A1
公开(公告)日：2013-06-20
申请号：US13328393
申请日：2011-12-16
申请人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
发明人： Gabriel H. LOH , James M. O'Connor , Michael Ignatowski , Nuwan S. Jayasena , Bradford M. Beckmann
CPC分类号： G11C5/02 , G06F11/1048
摘要： According to one embodiment, a memory architecture implemented method is provided, where the memory architecture includes a logic chip and one or more memory chips on a single die, and where the method comprises: reading values of data from the one or more memory chips to the logic chip, where the one or more memory chips and the logic chip are on a single die; modifying, via the logic chip on the single die, the values of data; and writing, from the logic chip to the one or more memory chips, the modified values of data.
摘要翻译： 根据一个实施例，提供了一种存储器架构实现的方法，其中存储器架构包括逻辑芯片和单个管芯上的一个或多个存储器芯片，并且其中该方法包括：从一个或多个存储器芯片读取数据的值 逻辑芯片，其中一个或多个存储器芯片和逻辑芯片在单个芯片上; 通过单个芯片上的逻辑芯片修改数据的值; 并从逻辑芯片向一个或多个存储器芯片写入修改的数据值。
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公开(公告)号：US08028290B2
公开(公告)日：2011-09-27
申请号：US11468547
申请日：2006-08-30
CPC分类号： G06F9/45533 , G06F9/30181 , G06F9/3885 , G06F9/5077 , G06F12/0802 , G06F15/7842 , G06F2209/507 , G06F2212/1028 , Y02D10/13 , Y02D10/22 , Y02D10/26 , Y02D10/28 , Y02D10/36
摘要： Multiple instruction set architectures are supported in a system that provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). A processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. A hypervisor controls operation of the cores, locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received. The ISA may be specified by a particular operating system and/or application program requirements.
摘要翻译： 在为多个指令集架构（ISA）需要多重支持的虚拟机环境中提供功率高效灵活的平台的系统中支持多指令集架构。 处理器包括具有不同的本机ISA的多个核，并且可以选择性地启用操作，以便当对处理器不需要对特定ISA的支持时，节省功率。 虚拟机管理程序控制核心的操作，定位核心，并在必要时启用实例化具有指定ISA的虚拟机的请求。 ISA可以由特定的操作系统和/或应用程序要求来指定。
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9.发明申请System and Computer Program Product for Dynamically Managing Power in MicroProcessor Chips According to Present Processing Demands 有权根据当前处理要求，微处理器芯片动态管理系统和计算机程序产品公开(公告)号：US20080229128A1
公开(公告)日：2008-09-18
申请号：US12131507
申请日：2008-06-02
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/3203 , G06F1/3287 , G06F9/30101 , G06F9/3885 , Y02D10/171 , Y02D50/20
摘要： A method, system, and computer program product are disclosed for dynamically managing power in a microprocessor chip that includes physical hardware elements within the microprocessor chip. A process is selected to be executed. Hardware elements that are necessary to execute the process are then identified. The power in the microprocessor chip is dynamically altered by altering a present power state of the hardware elements that were identified as being necessary.
摘要翻译： 公开了一种方法，系统和计算机程序产品，用于在包括微处理器芯片内的物理硬件元件的微处理器芯片中动态管理电力。 选择执行一个进程。 然后识别执行该过程所需的硬件元素。 微处理器芯片中的电源通过改变被识别为必要的硬件元件的当前功率状态来动态地改变。
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10.发明申请Systems and methods for masking latency of memory reorganization work in a compressed memory system 失效用于屏蔽存储器重组延迟的系统和方法在压缩存储器系统中工作公开(公告)号：US20080059728A1
公开(公告)日：2008-03-06
申请号：US11516207
申请日：2006-09-06
申请人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
发明人： David Michael Daly , Peter Anthony Franaszek , Michael Ignatowski , Luis Alfonso Lastras-Montano , Michael Raymond Trombley
IPC分类号： G06F13/28
CPC分类号： G06F12/08 , G06F12/0804 , G06F12/1408 , G06F2212/401
摘要： Computer memory management systems and methods are provided in which data block buffering and priority scheduling protocols are utilized in compressed memory systems to mask the latency associated with memory reorganization work following access to compressed main memory. In particular, data block buffers and priority scheduling protocols are implemented to delay and prioritize memory reorganization work to allow resources to be used for serving new memory access requests and other high priority commands.
摘要翻译： 提供了计算机存储器管理系统和方法，其中在压缩存储器系统中利用数据块缓冲和优先级调度协议来掩盖在访问压缩主存储器之后与存储器重组工作相关联的等待时间。 特别地，实现数据块缓冲器和优先级调度协议以延迟和优先化存储器重组工作，以允许资源用于服务新的存储器访问请求和其他高优先级命令。
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