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1.发明授权Method for dose calculation of photolithography projection printers through bleaching of photo-active compound in a photoresist 失效通过在光致抗蚀剂中漂白光活性化合物来计算光刻投影打印机的方法
公开(公告)号：US4474864A
公开(公告)日：1984-10-02
申请号：US512281
申请日：1983-07-08
申请人： Ming-Fea Chow , Alexander D. Lopata , Christopher F. Lyons , Robert C. McIntosh , Anthony F. Scaduto
发明人： Ming-Fea Chow , Alexander D. Lopata , Christopher F. Lyons , Robert C. McIntosh , Anthony F. Scaduto
CPC分类号： G03F7/70558 , G03F7/105 , G03F7/20
摘要： A process for setting the exposure speed of photolithography instruments is described, using a method of dosimetry based on photoactive compound bleaching of photoresist. A curve of light absorbance to exposure speed and a calibration curve of light absorbance to dose are determined for a photoresist. The exposure speed for any desired degree of resist bleaching can be set using the first curve, and the exposure speed for a predetermined dosage can be set by determining the common light absorbance value on the exposure speed and dosage curves.
摘要翻译： 使用基于光致抗蚀剂的光活性化合物漂白的剂量测定方法来描述用于设定光刻仪的曝光速度的方法。 对于光致抗蚀剂，测定吸光度对曝光速度的曲线以及光吸收率与剂量的校准曲线。 可以使用第一曲线设定任何所需程度的抗蚀剂漂白的曝光速度，并且可以通过确定曝光速度和剂量曲线上的常见光吸收值来设定预定剂量的曝光速度。
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2.发明授权公开(公告)号：US07169711B1
公开(公告)日：2007-01-30
申请号：US10170984
申请日：2002-06-13
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337
摘要： A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.
摘要翻译： 使用碳间隔物进行临界尺寸减小的方法可以包括在基底上提供图案化的光致抗蚀剂层，其中图案化的光致抗蚀剂层具有第一宽度的孔，在光致抗蚀剂层上沉积碳膜并蚀刻沉积的碳膜以形成间隔物 在图案化光致抗蚀剂层的孔的侧壁上，使用所形成的间隔物和图案化的光致抗蚀剂层作为图案蚀刻衬底，以形成具有第二宽度的沟槽，并使用氧化蚀刻去除图案化的光致抗蚀剂层和形成的间隔物。
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3.发明授权SO2 treatment of oxidized CuO for copper sulfide formation of memory element growth 有权SO2处理氧化CuO对硫化铜形成记忆元素生长公开(公告)号：US07115440B1
公开(公告)日：2006-10-03
申请号：US10957247
申请日：2004-10-01
IPC分类号： H01L21/00
CPC分类号： H01L51/0575 , B82Y10/00 , G11C13/0014 , G11C13/0016 , G11C2213/77 , H01L27/285 , H01L51/105
摘要： Disclosed are methods of making memory cells and semiconductor devices containing the memory cells. The methods involve oxidizing a portion of a copper containing electrode to form a copper oxide layer; contacting the copper oxide layer with at least one of a sulfur containing gas or plasma to form a CuS layer; forming an organic semiconductor over the CuS layer; and forming an electrode over the organic semiconductor. Such devices containing the memory cells are characterized by light weight and robust reliability.
摘要翻译： 公开了制造存储单元和包含存储单元的半导体器件的方法。 所述方法包括氧化一部分含铜电极以形成氧化铜层; 使所述氧化铜层与含硫气体或等离子体中的至少一种接触以形成CuS层; 在CuS层上形成有机半导体; 并在有机半导体上形成电极。 包含存储器单元的这种器件的特征在于重量轻和鲁棒的可靠性。
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4.发明授权Negative resist or dry develop process for forming middle of line implant layer 有权用于形成线植入层中间的负阻抗或干式显影工艺公开(公告)号：US07112489B1
公开(公告)日：2006-09-26
申请号：US11004691
申请日：2004-12-03
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L27/115 , H01L21/26513 , H01L27/11521
摘要： A method of implanting a middle of line (MOL) implant layer of a flash memory device that does not require a descumming step is disclosed. In a first embodiment, the method includes depositing a negative tone resist over the MOL implant layer. Portions of the negative tone resist in and above a plurality of trenches are not exposed to optical radiation, while portions surrounding the plurality of trenches are exposed. The unexposed portions are developed out thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step. In a second embodiment, a bi-layer resist is deposited on the MOL implant layer, wherein the bi-layer resist includes a silicon containing top layer and a bottom layer. The bi-layer resist is patterned to expose a portion of the bottom layer that resides in and above a plurality of trenches. The bottom layer is dry etch developed using oxygen plasma as the etchant, thereby leaving a bottom surface of each trench substantially free of a resist residue. Implants can be placed in the MOL implant layer without the need for a descumming step.
摘要翻译： 公开了一种注入不需要除尘步骤的闪速存储器件的中间线（MOL）注入层的方法。 在第一实施例中，该方法包括在MOL植入层上沉积负色调抗蚀剂。 在多个沟槽中和上方的负色调抗蚀剂的部分不暴露于光辐射，而围绕多个沟槽的部分被暴露。 未曝光部分显影出来，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。 植入物可以放置在MOL植入层中，而不需要除去步骤。 在第二实施例中，双层抗蚀剂沉积在MOL注入层上，其中双层抗蚀剂包括含硅顶层和底层。 图案化双层抗蚀剂以暴露驻留在多个沟槽中和上方的底层的一部分。 底层是使用氧等离子体作为蚀刻剂进行干法蚀刻，从而留下每个沟槽的底表面基本上没有抗蚀剂残留物。 植入物可以放置在MOL植入层中，而不需要除去步骤。
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公开(公告)号：US07018922B1
公开(公告)日：2006-03-28
申请号：US10968713
申请日：2004-10-19
IPC分类号： H01L21/4763
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115
摘要： A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.
摘要翻译： 公开了一种在闪速存储器件中形成触点的方法。 该方法增加了接触和层叠栅极层之间的焦距裕度和覆盖边缘的深度。 在半导体衬底上形成多个层叠的栅极层，其中每个堆叠的栅极层沿预定的方向延伸并且基本上平行于其它堆叠的栅极层。 层叠绝缘层沉积在多个堆叠的栅极层上，并且在多个堆叠的栅极层的第一堆叠的栅极层和多个堆叠的栅极层的第二叠层栅极层之间形成接触孔。 接触孔形成为细长形状，其中接触孔的长轴基本上平行于堆叠的栅极层。 导电层沉积在接触孔中，去除过量的导电材料。
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公开(公告)号：US06869888B1
公开(公告)日：2005-03-22
申请号：US09901704
申请日：2001-07-11
IPC分类号： H01L21/027 , H01L21/3105 , H01L21/312 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/02118 , H01L21/0212 , H01L21/02134 , H01L21/0276 , H01L21/31058 , H01L21/312 , H01L21/76825
摘要： A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.
摘要翻译： 对半导体装置的形成方法进行说明。 该方法包括在半导体衬底上形成第一层。 通过第一层形成至少一个孔。 在至少一个孔中形成底部抗反射涂层（BARC）层。 BARC层暴露于电子束（电子束），使得BARC层在至少一个孔中达到流动温度。 执行蚀刻以在第一层中和在至少一个孔上形成沟槽，其中至少一个孔中的BARC层在蚀刻期间用作耐蚀刻层。
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公开(公告)号：US06808591B1
公开(公告)日：2004-10-26
申请号：US10021531
申请日：2001-12-12
申请人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
发明人： Khoi A. Phan , Bharath Rangarajan , Christopher F. Lyons , Steven C. Avanzino , Ramkumar Subramanian , Bhanwar Singh , Cyrus E. Tabery
IPC分类号： H01L21302
CPC分类号： H01L21/67253 , H01L21/32136
摘要： A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.
摘要翻译： 提供了用于金属过程控制的系统和方法。 通过利用过滤设备模型来确定金属过蚀刻过程以确定过蚀刻时间或过程延伸端点。 系统和方法减少了手动测试和手动过程表征的需要。 一种过蚀系统包括金属蚀刻机，目标装置和过程控制器。 目标设备位于金属蚀刻机中或其上。 该过程控制器耦合到金属蚀刻器。 过程控制器通过金属蚀刻器控制目标器件的过蚀刻。 该过程控制器包括一个过时延时间控制器，一组蚀刻控制模型和一个控制系统。
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公开(公告)号：US06773954B1
公开(公告)日：2004-08-10
申请号：US10313494
申请日：2002-12-05
申请人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
发明人： Ramkumar Subramanian , Jane V. Oglesby , Sergey D. Lopatin , Mark S. Chang , Christopher F. Lyons , James J. Xie , Minh Van Ngo
IPC分类号： H01L5140
CPC分类号： G11C13/0014 , B82Y10/00 , G11C13/0016 , H01L27/28 , H01L51/0034 , H01L51/0035 , H01L51/0036 , H01L51/0037 , H01L51/0043 , H01L51/0053 , H01L51/0059 , H01L51/0062 , H01L51/0077 , H01L51/0078 , H01L51/0081 , H01L51/0085
摘要： Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.
摘要翻译： 公开了在两个电极之间制造由具有可控导电介质的两个电极制成的有机存储单元的方法。 可控导电介质包含有机半导体层和无源层。 特别地，描述了形成电极和相邻钝化层的新颖方法。
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公开(公告)号：US06764949B2
公开(公告)日：2004-07-20
申请号：US10334392
申请日：2002-12-30
申请人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
发明人： Douglas J. Bonser , Marina V. Plat , Chih Yuh Yang , Scott A. Bell , Darin Chan , Philip A. Fisher , Christopher F. Lyons , Mark S. Chang , Pei-Yuan Gao , Marilyn I. Wright , Lu You , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2144
CPC分类号： H01L21/32139 , H01L21/0332
摘要： A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning. The lowest layer of the hardmask stack is preferably amorphous carbon to facilitate easy removal of the hardmask stack from underlying materials by an ashing process.
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10.发明授权Process for etching an organic dielectric using a silyated photoresist mask 有权使用硅化光致抗蚀剂掩模蚀刻有机电介质的方法公开(公告)号：US06660645B1
公开(公告)日：2003-12-09
申请号：US10051725
申请日：2002-01-17
IPC分类号： H07L21302
CPC分类号： H01L21/31144
摘要： A process for forming a semiconductor device may comprise forming an organic dielectric layer on a substrate, forming a protective layer on the organic dielectric layer, forming a photoresist mask on the protective layer, and silyating the photoresist mask. The protective layer is etched using the silyated photoresist mask as an etch mask, and then the organic dielectric layer is etched using the silyated photoresist mask as an etch mask. Metal may be deposited in a void etched in the organic dielectric layer to form a wiring, contact or via.
摘要翻译： 用于形成半导体器件的工艺可以包括在衬底上形成有机电介质层，在有机介电层上形成保护层，在保护层上形成光致抗蚀剂掩模，并使光刻胶掩模进行硅化。 使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻保护层，然后使用硅化光致抗蚀剂掩模作为蚀刻掩模蚀刻有机介电层。 金属可以沉积在蚀刻在有机介电层中的空隙中以形成布线，接触或通孔。
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