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    Methods for making high performance lateral bipolar transistors
    1.
    发明授权
    Methods for making high performance lateral bipolar transistors 失效
    制造高性能横向双极晶体管的方法

    公开(公告)号：US4492008A

    公开(公告)日：1985-01-08

    申请号：US520366

    申请日：1983-08-04

    申请人： Narasipur G. Anantha ,  Tak H. Ning ,  Paul J. Tsang

    发明人： Narasipur G. Anantha ,  Tak H. Ning ,  Paul J. Tsang

    IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L27/08 ,  H01L21/76

    CPC分类号： H01L29/6625 ,  H01L21/743 ,  H01L21/8224 ,  H01L27/0821 ,  H01L29/735

    摘要： A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove. The P+ polycrystalline silicon layer is then formed on the surface which will in turn fill the groove with this material. The heating of the structure forms the P+ emitter region around the side edges of the P+ polycrystalline silicon filled groove. The P+ polycrystalline layer is the emitter contact, the N+ reach-through connected through the buried N+ region is the base contact and the collector contact is made to the P-type collector region.

    摘要翻译： 可以通过首先提供具有主表面的单晶半导体主体并且其中期望的晶体管是PNP晶体管，具有将掩埋区域连接到所述主表面的N +到达通孔的掩埋N +区域来制造高性能横向晶体管。 晶体管的集电极区域通过将P型杂质铺展成期望的区域而形成为表面。 绝缘层形成在半导体本体的顶表面上。 在需要沟槽或沟道 - 发射极接触的绝缘层中形成开口。 使用图案化绝缘层作为蚀刻掩模，将基本垂直的壁槽蚀刻到单晶半导体本体中。 进行N基扩散以在体内的开口的周边周围产生N区。 然后将氧离子注入凹槽的底部，以在凹槽的底部形成二氧化硅区域。 然后在表面上形成P +多晶硅层，该表面依次用该材料填充凹槽。 结构的加热在P +多晶硅填充槽的侧边缘周围形成P +发射极区域。 P +多晶层是发射极接触，通过埋入N +区连接的N +到达通孔是基极接触，并且集电极接触到P型集电极区域。

    SOI LATERAL BIPOLAR TRANSISTOR HAVING MULTI-SIDED BASE CONTACT AND METHODS FOR MAKING SAME
    6.
    发明申请
    SOI LATERAL BIPOLAR TRANSISTOR HAVING MULTI-SIDED BASE CONTACT AND METHODS FOR MAKING SAME 有权
    具有多面基底接触的SOI侧向双极晶体管及其制造方法

    公开(公告)号：US20130168821A1

    公开(公告)日：2013-07-04

    申请号：US13343688

    申请日：2012-01-04

    申请人： Jin Cai ,  Tak H. Ning

    发明人： Jin Cai ,  Tak H. Ning

    IPC分类号： H01L27/082 ,  H01L21/328 ,  H01L29/70

    CPC分类号： H01L27/082 ,  H01L21/8249 ,  H01L29/1004 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/6625 ,  H01L29/735

    摘要： A Bipolar Junction Transistor with an intrinsic base, wherein the intrinsic base includes a top surface and two side walls orthogonal to the top surface, and a base contact electrically coupled to the side walls of the intrinsic base. In one embodiment an apparatus can include a plurality of Bipolar Junction Transistors, and a base contact electrically coupled to the side walls of the intrinsic bases of each BJT.

    摘要翻译： 一种具有本征基极的双极结晶体管，其中本征基极包括顶表面和与顶表面正交的两个侧壁，以及电耦合到本征基底的侧壁的基部接触。 在一个实施例中，装置可以包括多个双极结晶体管，以及电耦合到每个BJT的内部基极的侧壁的基部触点。

    Junction Field Effect Transistor With An Epitaxially Grown Gate Structure
    9.
    发明申请
    Junction Field Effect Transistor With An Epitaxially Grown Gate Structure 失效
    具有外延生长门结构的结场效应晶体管

    公开(公告)号：US20120256238A1

    公开(公告)日：2012-10-11

    申请号：US13080690

    申请日：2011-04-06

    申请人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Tak H. Ning ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/808 ,  H01L21/337

    CPC分类号： H01L29/812 ,  H01L21/84 ,  H01L21/845 ,  H01L27/098 ,  H01L27/1203 ,  H01L29/66545 ,  H01L29/66848 ,  H01L29/66893 ,  H01L29/785 ,  H01L29/808

    摘要： A method of fabricating a semiconductor device that includes forming a replacement gate structure on a portion of a semiconductor substrate, wherein source regions and drain regions are formed in opposing sides of the replacement gate structure. A dielectric is formed on the semiconductor substrate having an upper surface that is coplanar with an upper surface of the replacement gate structure. The replacement gate structure is removed to provide an opening to an exposed portion of the semiconductor substrate. A functional gate conductor is epitaxially grown within the opening in direct contact with the exposed portion of the semiconductor substrate. The method is applicable to planar metal oxide semiconductor field effect transistors (MOSFETs) and fin field effect transistors (finFETs).

    摘要翻译： 一种制造半导体器件的方法，包括在半导体衬底的一部分上形成替换栅极结构，其中源极区和漏极区形成在替换栅极结构的相对侧。 在具有与替换栅极结构的上表面共面的上表面的半导体衬底上形成电介质。 去除替代栅极结构以提供对半导体衬底的暴露部分的开口。 功能栅极导体在开口内外延生长，与半导体衬底的暴露部分直接接触。 该方法适用于平面金属氧化物半导体场效应晶体管（MOSFET）和鳍式场效应晶体管（finFET）。

    HORIZONTAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR
    10.
    发明申请
    HORIZONTAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR 有权
    水平多晶硅锗绝缘双极晶体管

    公开(公告)号：US20120235151A1

    公开(公告)日：2012-09-20

    申请号：US13048342

    申请日：2011-03-15

    申请人： Jin Cai ,  Kevin K. Chan ,  Wilfried W. Haensch ,  Tak H. Ning

    发明人： Jin Cai ,  Kevin K. Chan ,  Wilfried W. Haensch ,  Tak H. Ning

    IPC分类号： H01L29/737 ,  H01L21/331

    CPC分类号： H01L29/737 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/66265

    摘要： A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.

    摘要翻译： 水平异质结双极晶体管（HBT）包括具有第一导电类型的掺杂的掺杂单晶Ge作为具有约0.66eV的能带隙的基极，以及掺杂有第二导电类型的掺杂多晶硅作为宽间隙 - 发射体具有约1.12eV的能带隙。 在一个实施例中，采用具有第二导电类型掺杂的掺杂多晶硅作为集电极。 在其它实施例中，采用具有第二导电类型掺杂的单晶Ge作为集电极。 在这样的实施例中，由于基极和集电极包括具有相同晶格常数的相同的半导体材料即Ge，所以在集电极和基极之间不存在晶格失配问题。 在两个实施例中，由于发射极是多晶的并且基极是单晶的，所以在基极和发射极之间不存在晶格失配问题。