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    Semiconductor device and lead frame therefor
    1.
    发明授权
    Semiconductor device and lead frame therefor 有权

    公开(公告)号：US10256168B2

    公开(公告)日：2019-04-09

    申请号：US15180072

    申请日：2016-06-12

    Applicant: Nexperia B.V.

    Inventor： Shun Tik Yeung ,  Pompeo V. Umali ,  Chi Ho Leung ,  Kan Wae Lam ,  Hans-Juergen Funke ,  Shu-Ming Yip

    IPC: H01L23/367 ,  H01L23/373 ,  H05K1/02 ,  H05K7/10 ,  H05K7/20 ,  H01L23/495 ,  H01L23/00

    Abstract: A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second terminals. A lead frame has a first part and a second part. The second part of the lead frame is both electrically and mechanically spaced from the first part. The second side of the die is attached to the lead frame such that the first and second lead frame parts are respectively connected to the at least two second terminals. The first and second lead frame parts include respective first and second extensions that project past a side of the die and provide first and second terminal surfaces that are co-planar with the first terminal on the first side of the die. The device makes use of the terminals on the both sides of the die. The device second side is exposed for thermal performance.

    Semiconductor device and method of manufacture
    2.
    发明授权
    Semiconductor device and method of manufacture 有权

    公开(公告)号：US11094562B2

    公开(公告)日：2021-08-17

    申请号：US16220125

    申请日：2018-12-14

    Applicant: NEXPERIA B.V.

    Inventor： Leung Chi Ho ,  Pompeo V. Umali ,  Shun Tik Yeung

    IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.

    Reversible semiconductor die
    4.
    发明授权
    Reversible semiconductor die 有权

    公开(公告)号：US10262926B2

    公开(公告)日：2019-04-16

    申请号：US15286444

    申请日：2016-10-05

    Applicant: Nexperia B.V.

    Inventor： Kan Wae Lam ,  Harrie Martinus Maria Horstink ,  Sven Walczyk ,  Chi Ho Leung ,  Thierry Jans ,  Pompeo V. Umali ,  Shun Tik Yeung

    IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00

    Abstract: A semiconductor die has internal circuitry formed on two more internal layers, and die bonding pads arranged on a top surface of the die. The bonding pads are connected to the internal circuitry for providing input and output signals to the internal circuitry. One or more connecting lines electrically connect one or more pairs of the die bonding pads, thereby defining a bonding pad layout. The die bonding pads are arranged and connected with the connecting lines such that the bonding pad layout is reversible, which allows the die to be used in different package types (e.g., TSSOP or DFN) yet maintain a standardized pin arrangement without the necessity for long or crossed bond wires.

    Electronic device
    5.
    发明授权
    Electronic device 有权

    公开(公告)号：US10658274B2

    公开(公告)日：2020-05-19

    申请号：US16221723

    申请日：2018-12-17

    Applicant: NEXPERIA B.V.

    Inventor： Tim Boettcher ,  Haibo Fan ,  Wai Wong Chow ,  Pompeo V. Umali ,  Shun Tik Yeung ,  Chi Ho Leung

    IPC: H01L21/00 ,  H01L23/495 ,  H01L23/00

    Abstract: An electronic device including a die and at least one lead. The electronic device further includes a corresponding at least one connector, each connector for connecting the die to a corresponding lead or leads, and each connector having a first end disposed in bondable proximity to a complementary surface of the corresponding lead and a second end disposed in bondable proximity to a complementary surface of the die. An end portion of at least one of the first end and second end has a formation, the formation in combination with the complementary surface of one, or both, of the respective lead or the die defining therebetween a first region and at least a second region configured to attract by capillary action an electrically conductive bonding material to consolidate therein.

    Wafer level semiconductor device with wettable flanks
    9.
    发明授权
    Wafer level semiconductor device with wettable flanks 有权

    公开(公告)号：US10410941B2

    公开(公告)日：2019-09-10

    申请号：US15259063

    申请日：2016-09-08

    Applicant: Nexperia B.V.

    Inventor： Chi Ho Leung ,  Pompeo V. Umali ,  Shun Tik Yeung ,  Kan Wae Lam

    IPC: H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/552 ,  H01L21/683 ,  H01L23/14

    Abstract: A semiconductor device includes a semiconductor die having a top surface that has one or more electrical contacts formed thereon, and an opposite bottom surface. A molding material encapsulates the top surface and at least a part of a side surface of the semiconductor die. The molding material defines a package body that has a top surface and a side surface. Openings are formed on the top surface of the package body, and the electrical contacts are partially exposed from the molding material through the openings. A metal layer is formed over and electrically connected to the electrical contacts through the openings. The metal layer extends to and at least partially covers the side surface of the package body.

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