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公开(公告)号：USRE34887E
公开(公告)日：1995-03-28
申请号：US683199
申请日：1991-04-10
IPC分类号： H01L23/538 , C03C3/066 , C03C3/093 , H01L23/498 , H05K1/03 , H05K3/46 , H05K1/09 , H05K1/16
CPC分类号： C03C3/066 , C03C3/093 , H01L23/49833 , H01L23/49894 , H05K1/0306 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/09701 , H01L2924/15312 , H05K3/4629 , Y10T29/49155 , Y10T29/4916
摘要： A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.
摘要翻译： 一种陶瓷多层电路板，包括交替层叠的陶瓷层和布线导体层，其中陶瓷层的热膨胀系数低于布线导体的热膨胀系数，不低于导体层的热膨胀系数的一半，并且由玻璃形成 其在不高于布线导体层的熔点的温度下软化; 在其焊接部分具有高可靠性的半导体模块，包括安装有安装有半导体器件的陶瓷载体衬底的所述陶瓷多层电路板，所述板可以使用具有良好导电性的银或铜导体; 和用于所述陶瓷多层电路板的无定形玻璃粉末。
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公开(公告)号：US4821142A
公开(公告)日：1989-04-11
申请号：US58255
申请日：1987-06-04
IPC分类号： H01L23/538 , C03C3/066 , C03C3/093 , H01L23/498 , H05K1/03 , H05K3/46
CPC分类号： C03C3/066 , C03C3/093 , H01L23/49833 , H01L23/49894 , H05K1/0306 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/09701 , H01L2924/15312 , H05K3/4629 , Y10T29/49155 , Y10T29/4916
摘要： A ceramic multilayer circuit board comprising ceramic layers and wiring conductor layers laminated alternately, in which the ceramic layer has a thermal expansion coefficient lower than that of the wiring conductor and not lower than one half of that of the conductor layer and is formed from a glass which softens at a temperature not higher than the melting point of the wiring conductor layer; a semiconductor module having a high reliability in its solder joint part comprising said ceramic multilayer circuit board mounted with a ceramic carrier substrate being mounted with a semiconductor device, said board being able to use a silver or copper conductor having a good electro-conductivity; and an amorphous glass powder for said ceramic multilayer circuit board.
摘要翻译： 一种陶瓷多层电路板，包括交替层叠的陶瓷层和布线导体层，其中陶瓷层的热膨胀系数低于布线导体的热膨胀系数，不低于导体层的热膨胀系数的一半，并且由玻璃形成 其在不高于布线导体层的熔点的温度下软化; 在其焊接部分具有高可靠性的半导体模块，包括安装有安装有半导体器件的陶瓷载体衬底的所述陶瓷多层电路板，所述板可以使用具有良好导电性的银或铜导体; 和用于所述陶瓷多层电路板的无定形玻璃粉末。
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3.发明授权
公开(公告)号：US4736276A
公开(公告)日：1988-04-05
申请号：US865396
申请日：1986-05-21
CPC分类号： H01L23/15 , C04B35/18 , H01L21/4807 , H01L2224/16 , H01L2224/16235 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01037 , H01L2924/01055 , H01L2924/01078 , H01L2924/01079 , H01L2924/15312 , H01L2924/15787 , H05K1/0306 , H05K3/4676 , Y10S428/901 , Y10T29/49163 , Y10T428/24322 , Y10T428/24917
摘要： Ceramic insulating substrate layers (1) for a multilayered ceramic wiring circuit board (3) consist essentially of crystals of mullite and sillimanite, non-crystalline silicon dioxide occupying the interstices between the crystals and magnesium oxide dissolved substantially in the crystals in solid solution and have a thermal expansion coefficient of 40-60.times.10.sup.-7 /.degree. C. and a dielectric constant below 6.7.
摘要翻译： 用于多层陶瓷布线电路板（3）的陶瓷绝缘基底层（1）基本上由莫来石和硅线石晶体组成，非结晶二氧化硅占据晶体间的空隙和基本上在固溶体中的晶体中溶解的氧化镁，并且具有 热膨胀系数为40-60×10-7 /℃，介电常数低于6.7。
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公开(公告)号：US4672152A
公开(公告)日：1987-06-09
申请号：US888410
申请日：1986-07-23
CPC分类号： H01L23/5383 , C03C10/0027 , H01L23/15 , H01L2224/16 , H01L2224/16235 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01055 , H01L2924/01079 , H01L2924/09701 , H01L2924/15312 , H05K1/0306 , H05K3/4629 , H05K3/4676 , Y10S428/901 , Y10T428/24926
摘要： A ceramic insulating layer (2) for the multilayer ceramic circuit board (11) consists of 60 wt % of crystallized glass and 40 wt % of a filler such as silicon dioxide bonded by the crystallized glass, which consists of 6-15 wt % of lithium oxide, 70-90 wt % of silicon dioxide, 1-8 wt % of aluminum oxide, 1-5 wt % of alkaline metal oxide other than lithium oxide and 2-5 wt % of alkaline earth metal oxide. The sintered ceramic insulating layer (2) has a dielectric constant below 6.1 and a flexural strength above 150 MPa and is co-firable with a wiring conductor layer of such as gold, silver and copper.
摘要翻译： 用于多层陶瓷电路板（11）的陶瓷绝缘层（2）由60重量％的结晶玻璃和40重量％的由结晶玻璃结合的填料如二氧化硅组成，其由6-15重量％ 氧化锂，70-90重量％的二氧化硅，1-8重量％的氧化铝，1-5重量％的除氧化锂以外的碱金属氧化物和2-5重量％的碱土金属氧化物。 烧结陶瓷绝缘层（2）的介电常数低于6.1，抗弯强度高于150MPa，与金，银和铜等布线导体层共存。
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公开(公告)号：US4825284A
公开(公告)日：1989-04-25
申请号：US940485
申请日：1986-12-10
申请人： Tasao Soga , Marahiro Goda , Fumio Nakano , Tadao Kushima , Nobuyuki Ushifusa , Fumiyuki Kobayashi , Mamoru Sawahata
发明人： Tasao Soga , Marahiro Goda , Fumio Nakano , Tadao Kushima , Nobuyuki Ushifusa , Fumiyuki Kobayashi , Mamoru Sawahata
IPC分类号： H01L23/52 , H01L21/56 , H01L21/60 , H01L23/433 , H01L23/473 , H01L23/498 , H01L23/538 , H01L25/11 , H01L39/02
CPC分类号： H01L24/81 , H01L21/563 , H01L23/4332 , H01L23/49827 , H01L23/5385 , H01L25/112 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/32245 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/81801 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10329 , H01L2924/15174 , H01L2924/15311 , H01L2924/15312 , H01L2924/15787 , H01L2924/18161 , H01L2924/3011 , H01L2924/351
摘要： A semiconductor resin package structure formed according to the flip-chip connection method and permitting to cool the rear surface of semiconductor chips, comprising semiconductor chip and carrier substrate which is soldered on one surface thereof to electrodes of the semiconductor chip according to the flip-chip connection method, the gap between the semiconductor chip and the carrier substrate being filled with resin having a thermal expansion coefficient, which is approximately equal to that of used solder, the electrodes of the semiconductor chip being electrically connected with terminals on the other surface of the carrier substrate through the soldered portions and a through-hole conductor disposed on the carrier substrate, the thermal expansion coefficient of the carrier substrate being approximately equal to that of a multi-layer substrate, with which the substrate is connected by soldering with the terminals.
摘要翻译： 根据倒装芯片连接方法形成的半导体树脂封装结构，并且允许冷却半导体芯片的背面，该半导体芯片包括半导体芯片和载体基板，该半导体芯片和载体基板在其一个表面上焊接到根据倒装芯片的半导体芯片的电极 连接方法中，半导体芯片和载体基板之间的间隙充满了热膨胀系数的树脂，其热膨胀系数近似等于使用的焊料的热膨胀系数，所述半导体芯片的电极与所述半导体芯片的另一表面上的端子电连接 通过焊接部分的载体衬底和布置在载体衬底上的通孔导体，载体衬底的热膨胀系数近似等于多层衬底的热膨胀系数，衬底通过与端子焊接而与其连接。
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6.发明授权
公开(公告)号：US4965660A
公开(公告)日：1990-10-23
申请号：US364537
申请日：1989-06-12
IPC分类号： H01L23/36 , H01L23/02 , H01L23/057 , H01L23/367 , H01L23/373
CPC分类号： H01L23/057 , H01L23/367 , H01L23/3737 , H01L2224/32188 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01079 , H01L2924/14 , H01L2924/16152 , H01L2924/16195
摘要： An integrated circuit package produced by bonding a rear surface of an insulating substrate enclosed in the package to a heat sink such as a cooling fin by a resinous adhesive, which may include one or more fillers, having a Young's modulus of 500 kg/cm.sup.2 or less when formed into a film, has high reliability at the bonding portion and withstands without damages even if subjected to thermal shocks.
摘要翻译： 一种集成电路封装件，其通过将包含在封装中的绝缘基板的后表面通过树脂粘合剂（例如可以包括一个或多个填料）的散热器（例如冷却翅片）结合，其杨氏模量为500kg / cm 2，或 在形成膜时较少，在接合部分具有高可靠性，并且即使遭受热冲击也能够承受损坏。
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7.发明授权
公开(公告)号：US4620264A
公开(公告)日：1986-10-28
申请号：US685133
申请日：1984-12-21
IPC分类号： H05K3/46 , C04B35/18 , H01L23/15 , H01L23/538 , H05K1/03
CPC分类号： H01L23/15 , C04B35/18 , H01L23/5383 , H05K1/0306 , H01L2224/16 , H01L2224/16235 , H01L2924/01014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15312 , H05K3/4629 , Y10T428/24917
摘要： A multi-layer ceramic wiring board consisting of alternately laminated ceramic insulating substrates and wiring conductor layers in which the inner-layer ceramic insulating substrates contacting the inside layers of signal wiring conductor are made of a ceramic insulator having a relative dielectric constant of 6.0 or below and a relatively low density and the ceramic insulating substrates of other layers are made of a ceramic insulator having a tensile strength of 4 kgf/mm.sup.2 or above and a relatively high density. In preparation of the board, each of the inner-layer ceramic insulating substrates is preferably formed from a green sheet obtained by drying a thin layer of a slurry containing 70 to 90 parts of ceramic filler particles having a particle size of 5 .mu.m or greater and 30 to 10 parts of glass powder while each of other ceramic insulating substrates is preferably formed from a green sheet obtained by drying a thin layer of a slurry containing 70 to 90 parts of ceramic filler particles having a particle size of less than 5 .mu.m and 30 to 10 parts of glass powder.
摘要翻译： 由交替层叠的陶瓷绝缘基板和布线导体层构成的多层陶瓷布线板，其中与信号布线导体的内层接触的内层陶瓷绝缘基板由相对介电常数为6.0以下的陶瓷绝缘体制成 并且其它层的陶瓷绝缘基板由拉伸强度为4kgf / mm 2以上且密度较高的陶瓷绝缘体制成。 在制备板时，每个内层陶瓷绝缘基板优选由通过干燥含有70至90份粒度为5μm或更大的陶瓷填料颗粒的浆料薄层而获得的生片形成 和30〜10份的玻璃粉末，而其它陶瓷绝缘基板中的每一个优选由通过干燥含有70-90份粒径小于5μm的陶瓷填料颗粒的浆料薄层而获得的生片形成 和30〜10份玻璃粉末。
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公开(公告)号：US4598167A
公开(公告)日：1986-07-01
申请号：US634066
申请日：1984-07-25
申请人： Nobuyuki Ushifusa , Satoru Ogihara , Takanobu Noro
发明人： Nobuyuki Ushifusa , Satoru Ogihara , Takanobu Noro
IPC分类号： B32B15/08 , B32B15/02 , H01L23/498 , H01L23/538 , H05K1/03 , H05K3/46 , H05K1/00
CPC分类号： H01L23/5384 , H01L23/49883 , H01L23/49894 , H05K1/0306 , H01L2224/16225 , H01L2924/09701 , H01L2924/15192 , H01L2924/15312
摘要： A multilayered ceramic circuit board, formed by sintering together a plurality of unit ceramic circuit boards, wherein each unit ceramic circuit board includes a ceramic layer, a patterned electrically conductive layer and through hole conductors formed in the ceramic layer for connecting the patterned electrically conductive layers of the respective unit ceramic circuit boards to form a predetermined wiring circuit. The patterned electrically conductive layers and the through hole conductors have a coefficient of thermal expansion which is greater than the coefficient of thermal expansion of the ceramic layers, wherein the difference between the coefficients of thermal expansion is selected to be less than 100.times.10.sup.-7 /.degree.C., and the through holes have decreased pitch. The conductive layers and conductors can be formed of a metal such as gold, silver or copper, with a low softening point glass filler to reduce the coefficient of thermal expansion of the conductive layers and conductors.The multilayered ceramic circuit board according to the present invention is less sensitive to cracks due to thermal stress.
摘要翻译： 一种多层陶瓷电路板，其通过将多个单元陶瓷电路板烧结在一起形成，其中每个单位陶瓷电路板包括陶瓷层，图案化导电层和形成在陶瓷层中的通孔导体，用于连接图案化的导电层 以形成预定的布线电路。 图案化的导电层和通孔导体的热膨胀系数大于陶瓷层的热膨胀系数，其中热膨胀系数之间的差选择为小于100×10 -7 /℃ C.，通孔的间距减小。 导电层和导体可以由诸如金，银或铜的金属与低软化点玻璃填料形成，以降低导电层和导体的热膨胀系数。 根据本发明的多层陶瓷电路板对于热应力对裂纹的敏感性较差。
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公开(公告)号：US4764233A
公开(公告)日：1988-08-16
申请号：US862169
申请日：1986-05-12
申请人： Satoru Ogihara , Nobuyuki Ushifusa
发明人： Satoru Ogihara , Nobuyuki Ushifusa
CPC分类号： H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/4629 , H05K3/4676
摘要： This invention provides a ceramic multi-layer circuit board wherein electroconductive patterns and ceramic insulating layers are piled alternately, characterized in that each ceramic insulating layer is a sintered product comprising one or more kinds of silica and a glass. Since the glass has a softening point lower than the melting point of the material of the electroconductive patterns, it enables sintering of the ceramic multi-layer circuit board at low temperatures. The silica is effective for reduction of the dielectric constant of each ceramic insulating layer.
摘要翻译： 本发明提供一种陶瓷多层电路板，其中导电图案和陶瓷绝缘层交替堆叠，其特征在于每个陶瓷绝缘层是包含一种或多种二氧化硅和玻璃的烧结产品。 由于玻璃的软化点低于导电图案的材料的熔点，所以能够在低温下烧结陶瓷多层电路板。 二氧化硅对于降低每个陶瓷绝缘层的介电常数是有效的。
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10.发明授权公开(公告)号：US07306346B2
公开(公告)日：2007-12-11
申请号：US11138469
申请日：2005-05-27
IPC分类号： F21V9/16
CPC分类号： H01L51/5259 , H01L51/5246 , H01L51/525
摘要： Inside surround desiccant pattern A surrounding an organic EL element by bonding an element substrate to a sealing board, outside surround desiccant pattern C surrounding the inside surround desiccant pattern A, and internal desiccant pattern (having a thinner film thickness than the inside surround desiccant pattern A) surrounded by the inside surround desiccant pattern A are formed on the sealing board by one time screen printing. For this purpose, a screen mask is utilized on which opening patterns for the inside and outside surround desiccant patterns A, C and an opening pattern having a narrower opening width than the opening patterns for A and C for forming an internal desiccant pattern are formed. With this configuration, it has been achieved to manufacture a highly reliable organic EL display apparatus in more simplified process.
摘要翻译： 围绕有机EL元件的内部环绕干燥剂图案A通过将元件基板粘合到密封板，围绕内部周围干燥剂图案A的外部周围干燥剂图案C和内部干燥剂图案（具有比内部环绕干燥剂图案A更薄的膜厚度） ）通过一次丝网印刷形成在密封板上由内部环绕干燥剂图案A包围。 为此，使用屏幕掩模，其中形成有用于内部和外部环绕干燥剂图案A，C的开口图案和具有比用于形成内部干燥剂图案的用于A和C的开口图案更窄的开口宽度的开口图案。 利用这种配置，已经实现了以更简化的方法制造高度可靠的有机EL显示装置。
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