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    Adaptive chuck for planar bonding between substrates
    2.
    发明授权
    Adaptive chuck for planar bonding between substrates 失效
    用于基板之间的平面粘合的自适应卡盘

    公开(公告)号：US08408262B2

    公开(公告)日：2013-04-02

    申请号：US12575968

    申请日：2009-10-08

    申请人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

    发明人： Dechao Guo ,  Fei Liu ,  Leathen Shi ,  Keith Kwong Hon Wong

    IPC分类号： B32B41/00

    CPC分类号： H01L21/6833 ,  B32B37/0007 ,  B32B2457/14 ,  Y10T156/1002

    摘要： An electrostatic chuck includes an array of independently biased conductive chuck elements, an array of sensor-conductor assemblies, and/or a combination of an array of sensor-conductor assemblies and at least one motorized chuck. Conductive chuck elements, either standing alone or embedded in a sensor-conductor assembly, are independently biased electrostatically to compensate for bowing and/or warping of a substrate thereupon so that the substrate can be bonded with a planar surface. A single electrostatic chuck can be employed to reduce the bowing and warping of one of the two substrates to be bonded, or two electrostatic chucks can be employed to minimize the bowing and warping of two substrates to be bonded.

    摘要翻译： 静电卡盘包括独立偏置的导电卡盘元件的阵列，传感器 - 导体组件的阵列，和/或传感器 - 导体组件阵列和至少一个电动卡盘的组合。 独立地或嵌入传感器 - 导体组件中的导电卡盘元件被静电地独立地偏置以补偿其上的衬底的弯曲和/或翘曲，使得衬底可以与平坦表面结合。 可以使用单个静电卡盘来减少要接合的两个基板中的一个的弯曲和翘曲，或者可以使用两个静电卡盘来最小化要接合的两个基板的弯曲和翘曲。

    LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION
    3.
    发明申请
    LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH SUBSEQUENT SELF ALIGNED SHALLOW TRENCH ISOLATION 有权
    具有后续自对准的双盒式背盖的低成本制造硅绝缘体波纹

    公开(公告)号：US20120112309A1

    公开(公告)日：2012-05-10

    申请号：US13350889

    申请日：2012-01-16

    申请人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

    发明人： Robert H. Dennard ,  David R. Greenberg ,  Amlan Majumdar ,  Leathen Shi ,  Jeng-Bang Yau

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/76275 ,  H01L21/76283 ,  H01L27/1203

    摘要： A semiconductor substrate structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer; an insulator with etch stop characteristics formed on the electrically conductive layer; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A scheme of subsequently building a dual-depth shallow trench isolation with the deeper STI in the back gate layer self-aligned to the shallower STI in the active region in such a semiconductor substrate is also disclosed.

    摘要翻译： 用于制造集成电路器件的半导体衬底结构包括块状衬底; 形成在所述本体基板上的下绝缘层，所述下绝缘层由一对具有接合界面的分离的绝缘层形成; 形成在下绝缘层上的导电层; 在所述导电层上形成具有蚀刻停止特性的绝缘体; 形成在所述蚀刻停止层上的上绝缘层; 以及形成在上绝缘层上的半导体层。 还公开了一种随后构建双深度浅沟槽隔离的方案，其中在与这种半导体衬底中的有源区域中较浅的STI自对准的背栅层中的较深STI相比较。

    Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
    5.
    发明授权
    Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) 失效
    拉伸应变SiGe绝缘体上的应变Si MOSFET（SGOI）

    公开(公告)号：US07485518B2

    公开(公告)日：2009-02-03

    申请号：US11684855

    申请日：2007-03-12

    申请人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

    发明人： Kevin K. Chan ,  Jack Q Chan ,  Kern Rim ,  Leathen Shi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78687 ,  H01L21/2007 ,  H01L29/1054 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/78603

    摘要： A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

    摘要翻译： 提供了用作形成高性能金属氧化物半导体场效应晶体管（MOSFET）器件的模板的半导体结构。 更具体地，本发明提供一种包括绝缘体上硅衬底的结构，其包括位于绝缘层顶部的拉伸应变SiGe合金层; 以及拉伸应变SiGe合金层顶部的应变Si层。 本发明还提供了形成拉伸应变SGOI基板以及上述异质结构的方法。 本发明的方法通过在绝缘层上直接提供拉伸应变SiGe合金层来分离应变Si层中的高应变和下层中的Ge含量的偏好。

    MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE
    7.
    发明申请
    MULTIPLE LAYER AND CYRSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
    多层和单层平面定向半导体基板

    公开(公告)号：US20080099844A1

    公开(公告)日：2008-05-01

    申请号：US11969320

    申请日：2008-01-04

    申请人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

    发明人： Toshiharu Furukawa ,  David Horak ,  Charles Koburger ,  Leathen Shi

    IPC分类号： H01L29/786

    CPC分类号： H01L29/045 ,  H01L21/76254 ,  H01L21/823807 ,  H01L27/1203

    摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.

    摘要翻译： 绝缘体上半导体衬底及其制造方法。 所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向， 第一晶体方向与第二晶体方向不同。

    SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer
    8.
    发明授权
    SOI wafers with 30-100 Å buried oxide (BOX) created by wafer bonding using 30-100 Å thin oxide as bonding layer 有权
    具有30-100埃埋层氧化物（BOX）的SOI晶片通过使用30-100薄氧化物作为结合层的晶片接合而产生

    公开(公告)号：US07166521B2

    公开(公告)日：2007-01-23

    申请号：US10957833

    申请日：2004-10-04

    申请人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

    发明人： Diane C. Boyd ,  Hussein I. Hanafi ,  Erin C. Jones ,  Dominic J. Schepis ,  Leathen Shi

    IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/21 ,  H01L21/36 ,  H01L21/425

    CPC分类号： H01L21/76251 ,  H01L21/76243

    摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

    摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

    Mechanical packaging and thermal management of flat mirror arrays
    10.
    发明授权
    Mechanical packaging and thermal management of flat mirror arrays 失效
    平面镜阵列的机械包装和热管理

    公开(公告)号：US5721602A

    公开(公告)日：1998-02-24

    申请号：US540860

    申请日：1995-10-11

    申请人： Chandrasekhar Narayan ,  Evan Colgan ,  Kei-Hsiung Yang ,  Robert L. Melcher ,  Lawrence S. Mok ,  Leathen Shi ,  Thomas M. Cipolla

    发明人： Chandrasekhar Narayan ,  Evan Colgan ,  Kei-Hsiung Yang ,  Robert L. Melcher ,  Lawrence S. Mok ,  Leathen Shi ,  Thomas M. Cipolla

    IPC分类号： G02F1/13 ,  G02F1/133 ,  G02F1/1333 ,  G02F1/136 ,  G09F9/00 ,  H04N5/74

    CPC分类号： G02F1/133385 ,  G02F1/133308 ,  G02F1/136 ,  G02F2001/133322 ,  G02F2001/133325

    摘要： A liquid crystal element, a packaging structure providing thermal and alignment control, a display device including the same, and methods of fabrication and assembly are provided. The liquid crystal element includes: a semiconductor wafer, having microcircuitry and an array of reflective pixels; a layer of electro-optical responsive liquid crystal medium, of uniform thickness, disposed on the reflective pixels; a transparent conductive layer positioned on the liquid crystal, being substantially parallel to the reflective layers, to ensure a uniform thickness of the liquid crystal; and an insulative transparent layer provided on the conductive layer. The liquid crystal element is laminated to an optically flat substrate to limit the out-of-plane distortions thereof. The structure formed by element and substrate are disposed in a substrate holder which is mounted to a wiring board, and coupled to voltage sources for actuating the liquid crystal. During mounting, an aligning fixture is used to ensure proper orientation of the element relative to the related optical elements. Once the element is positioned, a heat sink is coupled to the rear surface of the substrate holder to dissipate heat.

    摘要翻译： 提供液晶元件，提供热和对准控制的封装结构，包括该液晶元件的显示装置，以及制造和组装方法。 液晶元件包括：具有微电路的半导体晶片和反射像素阵列; 设置在反射像素上的均匀厚度的电光响应液晶介质层; 位于液晶上的透明导电层基本上平行于反射层，以确保液晶的均匀厚度; 以及设置在导电层上的绝缘透明层。 将液晶元件层压到光学平面基板上以限制其平面外失真。 由元件和基板形成的结构设置在安装到布线板上的基板保持器中，并连接到用于致动液晶的电压源。 在安装期间，使用对准夹具来确保元件相对于相关光学元件的正确取向。 一旦元件被定位，散热器耦合到衬底保持器的后表面以散热。