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    Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory
    3.
    发明授权
    Method for writing to the magnetoresistive memory cells of an integrated magnetoresistive semiconductor memory 失效
    写入集成磁阻半导体存储器的磁阻存储单元的方法

    公开(公告)号：US06897101B2

    公开(公告)日：2005-05-24

    申请号：US10685064

    申请日：2003-10-14

    申请人： Peter Weitz

    发明人： Peter Weitz

    IPC分类号： G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L21/338

    CPC分类号： G11C11/15 ,  H01L27/222

    摘要： An integrated magnetoresisitive semiconductor memory configuration has MRAM memory cells located at crossover points of selection lines that are embedded in different, mutually separate line planes. A read/write current can be impressed in respective selection lines for writing to each MRAM memory cell and for reading an information item written therein. In this magnetoresistive semiconductor memory configuration, selection lines that serve for reading a cell information item are in each case located in separate first and second line planes in direct contact with the memory cells. A third and a fourth line plane are spatially separated and electrically isolated from the first and second line planes and are occupied by write selection lines for writing a cell information item.

    摘要翻译： 集成的磁致电半导体存储器配置具有位于选择线的交叉点处的MRAM存储器单元，其被嵌入在不同的相互分离的线平面中。 可以在用于写入每个MRAM存储单元并用于读取其中写入的信息项的相应选择行中加上读/写电流。 在该磁阻半导体存储器配置中，用于读取单元信息项的选择线分别位于与存储单元直接接触的单独的第一和第二行平面中。 第三和第四行平面在空间上分离并且与第一和第二行平面电隔离，并且被用于写入单元信息项的写入选择线所占据。

    Circuit configuration for controlling the word lines of a memory matrix
    5.
    发明授权
    Circuit configuration for controlling the word lines of a memory matrix 有权

    公开(公告)号：US06608796B2

    公开(公告)日：2003-08-19

    申请号：US10114772

    申请日：2002-04-02

    申请人： Peter Weitz

    发明人： Peter Weitz

    IPC分类号： G11C800

    CPC分类号： G11C11/4085 ,  G11C8/08

    摘要： A circuit configuration for performing a selective changeover of word lines of a memory matrix between an activation potential and a deactivation potential uses selectively addressable drivers. The changeover of a word line input terminal from the activation potential to the deactivation potential is effected through the relevant driver if a deactivation signal is brought to an active state by a timing control circuit. In order to accelerate the deactivation of the word lines, a respectively assigned deactivation auxiliary switch is connected to each of the word lines at at least one terminal remote from the input terminal. The deactivation auxiliary switch is controlled by a timing control circuit such that it connects the remote terminal to the deactivation potential practically at the same instant at which the assigned driver changes the input terminal of the relevant word line from the activation potential over to the deactivation potential.