公开(公告)号：US08662941B2

公开(公告)日：2014-03-04

申请号：US13454317

申请日：2012-04-24

Applicant: Pravin Narwankar ,  Victor Pushparaj ,  Dieter Haas

Inventor： Pravin Narwankar ,  Victor Pushparaj ,  Dieter Haas

IPC: H01R4/16

CPC classification number: C23C16/52 ,  C23C16/44

Abstract: Apparatus for supporting the wires in a hot wire chemical vapor deposition (HWCVD) system are provided herein. In some embodiments, a terminal connector for a hot wire chemical vapor deposition (HWCVD) system may include a base; a wire clamp moveably disposed with relation to the base along an axis; a reflector shield extending from the wire clamp in a first direction along the axis; and a tensioner coupled to the base and wire clamp to bias the wire clamp in a second direction opposite the first direction.

Abstract translation: 本文提供了用于在热线化学气相沉积（HWCVD）系统中支撑电线的装置。 在一些实施例中，用于热线化学气相沉积（HWCVD）系统的终端连接器可以包括基座; 线夹，其相对于所述基部沿着轴线可移动地设置; 沿着所述轴线沿着第一方向从所述线夹延伸的反射器护罩; 以及张紧器，其联接到所述基座和线夹，以在与所述第一方向相反的第二方向偏置所述线夹。

公开(公告)号：US20060062917A1

公开(公告)日：2006-03-23

申请号：US11223896

申请日：2005-09-09

Applicant: Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

Inventor： Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

IPC: C23C16/00

CPC classification number: C23C16/308 ,  C23C16/401 ,  C23C16/56

Abstract: In one embodiment, a method for forming a morphologically stable dielectric material is provided which includes exposing a substrate to a hafnium precursor, a silicon precursor and an oxidizing gas to form hafnium silicate material during a chemical vapor deposition (CVD) process and subsequently and optionally exposing the substrate to a post deposition anneal, a nitridation process and a thermal annealing process. In some examples, the hafnium and silicon precursors used during a metal-organic CVD (MOCVD) process are alkylamino compounds, such as tetrakis(diethylamino)hafnium (TDEAH) and tris(dimethylamino)silane (Tris-DMAS). In another embodiment, other metal precursors may be used to form a variety of metal silicates containing tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof.

Abstract translation: 在一个实施方案中，提供了一种用于形成形态稳定的电介质材料的方法，其包括在化学气相沉积（CVD）工艺期间将衬底暴露于铪前体，硅前体和氧化气体以形成硅酸铪材料，随后和任选地 将衬底暴露于后沉积退火，氮化工艺和热退火工艺。 在一些实例中，在金属 - 有机CVD（MOCVD）方法中使用的铪和硅前体是烷基氨基化合物，例如四（二乙基氨基）铪（TDEAH）和三（二甲氨基）硅烷（Tris-DMAS）。 在另一个实施方案中，其它金属前体可用于形成含有钽，钛，铝，锆，镧或其组合的各种金属硅酸盐。

公开(公告)号：US20050260357A1

公开(公告)日：2005-11-24

申请号：US10851514

申请日：2004-05-21

Applicant: Christopher Olsen ,  Pravin Narwankar ,  Shreyas Kher ,  Randhir Thakur ,  Shankar Muthukrishnan ,  Philip Kraus

Inventor： Christopher Olsen ,  Pravin Narwankar ,  Shreyas Kher ,  Randhir Thakur ,  Shankar Muthukrishnan ,  Philip Kraus

IPC: C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  B05D7/00

CPC classification number: H01L21/3141 ,  C23C16/401 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/56 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31637 ,  H01L21/31645 ,  H01L29/517

Abstract: In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.

Abstract translation: 在一个实施例中，提供了一种在衬底上形成电介质堆叠的方法，其包括在衬底表面上沉积介电材料的第一层，将第一层暴露于氮化工艺，将第二层介电材料沉积在 第一层，将第二层暴露于氮化工艺，并将衬底暴露于退火工艺。 在另一个实施例中，提供了一种用于在衬底上形成介电材料的方法，其包括在衬底表面上沉积基本上不含硅的金属氧化物层，将金属氧化物层暴露于氮化工艺，以及将衬底暴露于退火工艺 。

公开(公告)号：US20050260347A1

公开(公告)日：2005-11-24

申请号：US10851561

申请日：2004-05-21

Applicant: Pravin Narwankar ,  Gregg Higashi

Inventor： Pravin Narwankar ,  Gregg Higashi

IPC: C23C16/30 ,  H01L21/314 ,  C23C16/00

CPC classification number: H01L21/3141 ,  C23C16/401 ,  H01L21/3143

Abstract: In one embodiment, a method for depositing a capping layer on a dielectric layer in a process chamber is provided which includes depositing the dielectric layer on a substrate surface, depositing a silicon-containing layer by an ALD process, comprising alternately pulsing a silicon precursor and an oxidizing gas into the process chamber, and exposing the silicon-containing layer to a nitridation process. In another embodiment, a method for depositing a silicon-containing capping layer on a dielectric layer in a process chamber by an ALD process is provided which includes flowing a silicon precursor into the process chamber, purging the process chamber with a purge gas, flowing an oxidizing gas comprising water formed by flowing a H2 gas and an oxygen-containing gas through a water vapor generator, and purging the process chamber with the purge gas.

Abstract translation: 在一个实施例中，提供了一种用于在处理室中的电介质层上沉积覆盖层的方法，其包括在基底表面上沉积电介质层，通过ALD工艺沉积含硅层，包括交替地脉冲硅前体和 氧化气体进入处理室，并将含硅层暴露于氮化过程。 在另一个实施例中，提供了一种通过ALD工艺在处理室中的电介质层上沉积含硅覆盖层的方法，其包括使硅前体流入处理室，用净化气体吹扫处理室， 包括通过使H 2气体和含氧气体流过水蒸气发生器而形成的水的氧化气体，以及用吹扫气体吹扫处理室。

公开(公告)号：US06548368B1

公开(公告)日：2003-04-15

申请号：US09644941

申请日：2000-08-23

Applicant: Pravin Narwankar ,  Ravi Rajagopalan

Inventor： Pravin Narwankar ,  Ravi Rajagopalan

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185

Abstract: Provided is a method of integrating Ta2O5 into an MIS stack capacitor for a semiconductor device by forming a thin SiON layer at the Si/TaO interface using low temperature remote plasma oxidation anneal. Also provided is a method of forming an MIS stack capacitor with improved electrical performance by treating SiO2 with remote plasma nitridation or SiN layer with rapid thermal oxidation or RPO to form a SiON layer prior to Ta2O5 deposition with TAT-DMAE, TAETO or any other Ta-containing precursor.

Abstract translation: 提供了一种通过使用低温远程等离子体氧化退火在Si / TaO界面处形成薄SiON层来将Ta 2 O 5集成到用于半导体器件的MIS堆叠电容器中的方法。 还提供了一种通过用远程等离子体氮化处理SiO 2或具有快速热氧化或RPO的SiN层来形成具有改进的电性能的MIS堆叠电容器的方法，以在与TAT-DMAE，TAETO或任何其它Ta的Ta 2 O 5沉积之前形成SiON层 含有前体。

公开(公告)号：US20070049043A1

公开(公告)日：2007-03-01

申请号：US11209472

申请日：2005-08-23

Applicant: Shankar Muthukrishnan ,  Rahul Sharangpani ,  Tejal Goyani ,  Pravin Narwankar ,  Shreyas Kher ,  Yi Ma ,  Giuseppina Conti

Inventor： Shankar Muthukrishnan ,  Rahul Sharangpani ,  Tejal Goyani ,  Pravin Narwankar ,  Shreyas Kher ,  Yi Ma ,  Giuseppina Conti

IPC: H01L21/31

CPC classification number: H01L21/0234 ,  H01L21/02329 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/31645 ,  H01L29/517

Abstract: A method and apparatus for forming a nitrided gate dielectric. The method comprises incorporating nitrogen into a dielectric film using a plasma nitridation process to form a nitrided gate dielectric. The first step involves providing a substrate comprising a gate dielectric film. The second step involves inducing a voltage on the substrate. Finally, the substrate is exposed to a plasma comprising a nitrogen source while maintaining the voltage to form a nitrided gate dielectric on the substrate. In one embodiment, the voltage is induced on the substrate by applying a voltage to an electrostatic chuck supporting the substrate. In another embodiment, the voltage is induced on the substrate by applying a DC bias voltage to an electrode positioned adjacent the substrate.

Abstract translation: 一种用于形成氮化栅极电介质的方法和装置。 该方法包括使用等离子体氮化工艺将氮合并到电介质膜中以形成氮化栅极电介质。 第一步涉及提供包括栅介质膜的衬底。 第二步涉及在衬底上感应电压。 最后，将衬底暴露于包含氮源的等离子体，同时保持电压以在衬底上形成氮化栅电介质。 在一个实施例中，通过向支撑衬底的静电卡盘施加电压来在衬底上感应电压。 在另一个实施例中，通过对邻近衬底定位的电极施加DC偏置电压来在衬底上感应出电压。

公开(公告)号：US06617266B2

公开(公告)日：2003-09-09

申请号：US09834698

申请日：2001-04-12

Applicant: Annabel Susan Nickles ,  Ravi Rajagopalan ,  Pravin Narwankar

Inventor： Annabel Susan Nickles ,  Ravi Rajagopalan ,  Pravin Narwankar

IPC: H01L2131

CPC classification number: C23C16/56 ,  H01L21/3105

Abstract: A process for forming high k dielectric thin films on a substrate, e.g., silicon, by 1) low temperature (500° C. or less) deposition of a dielectric material onto a surface, followed by 2) high temperature post-deposition annealing. The deposition can take place in an oxidative environment, followed by annealing, or alternatively the deposition can take place in a non-oxidative environment (e.g., N2), followed by oxidation and annealing.

Abstract translation: 1）通过1）将电介质材料沉积在表面上，然后2）高温后沉积退火，在衬底（例如硅）上形成高k电介质薄膜的方法，即1）低温（500℃或更低）。 沉积可以在氧化环境中进行，随后退火，或者沉积可以在非氧化环境（例如，N 2）中进行，随后进行氧化和退火。

公开(公告)号：US06518203B2

公开(公告)日：2003-02-11

申请号：US10002654

申请日：2001-10-18

Applicant: Pravin Narwankar ,  Turgut Sahin

Inventor： Pravin Narwankar ,  Turgut Sahin

IPC: H01L21469

CPC classification number: H01L21/7687 ,  H01L28/40

Abstract: The present invention describes a method of processing a substrate. According to the present invention a dielectric layer is formed on the substrate. The dielectric layer is then exposed in a first chamber to activated nitrogen atoms formed in a second chamber to form a nitrogen passivated dielectric layer. A metal nitride film is then formed on the nitrogen passivated dielectric layer.

公开(公告)号：US06217658B1

公开(公告)日：2001-04-17

申请号：US09328709

申请日：1999-06-09

Applicant: Maciek Orczyk ,  Laxman Murugesh ,  Pravin Narwankar

Inventor： Maciek Orczyk ,  Laxman Murugesh ,  Pravin Narwankar

IPC: C23C1600

CPC classification number: C23C16/463 ,  C03C3/06 ,  C03C2201/12 ,  C03C2203/46 ,  C23C16/401 ,  C23C16/46 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31625

Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate. This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers. An undoped silicon glass (USG) liner protects the substrate from corrosive attack. The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 0.8 &mgr;m with an aspect ratio of up to 4.5:1.

Abstract translation: 一系列工艺步骤在衬底上形成氟化硅玻璃（FSG）层。 该层在层中不太可能形成雾状或气泡，并且在后续处理步骤中比其他FSG层更不可能解吸水蒸汽。 未掺杂的硅玻璃（USG）衬垫可保护基材免受腐蚀性侵袭。 USG衬垫和FSG层沉积在相对热的晶片表面上，并且可以填充窄至0.8μm的衬底上的沟槽，纵横比高达4.5:1。

公开(公告)号：US5811356A

公开(公告)日：1998-09-22

申请号：US704428

申请日：1996-08-19

Applicant: Laxman Murugesh ,  Pravin Narwankar ,  Turgut Sahin ,  Kent Rossman

Inventor： Laxman Murugesh ,  Pravin Narwankar ,  Turgut Sahin ,  Kent Rossman

IPC: C23C16/44 ,  C23C16/50 ,  C23C16/517 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/00

CPC classification number: H01J37/32862 ,  C23C16/4401 ,  C23C16/4404 ,  C23C16/517 ,  H01J37/321 ,  Y10S438/905

Abstract: The present invention provides a method and apparatus for reducing the concentration of mobile ion and metal contaminants in a processing chamber by increasing the bias RF power density to greater than 0.051 W/mm.sup.2 and increasing the season time to greater than 30 seconds, during a chamber seasoning step. The method of performing a season step in a chamber by depositing a deposition material under the combined conditions of a bias RF power density of about 0.095 W/mm.sup.2 and a season time of from about 50 to about 70 seconds, reduces the mobile ion and metal contaminant concentrations within the chamber by about one order of magnitude.

Abstract translation: 本发明提供了一种通过在室内增加偏压RF功率密度大于0.051W / mm 2并将季节时间增加到大于30秒来减少处理室中的移动离子和金属污染物的浓度的方法和装置 调味步骤 通过在约0.095W / mm 2的偏置RF功率密度和约50至约70秒的季节时间的组合条件下沉积沉积材料在室中进行季节步骤的方法减少了移动离子和金属 室内的污染物浓度大约一个数量级。