公开(公告)号：US06217658B1

公开(公告)日：2001-04-17

申请号：US09328709

申请日：1999-06-09

Applicant: Maciek Orczyk ,  Laxman Murugesh ,  Pravin Narwankar

Inventor： Maciek Orczyk ,  Laxman Murugesh ,  Pravin Narwankar

IPC: C23C1600

CPC classification number: C23C16/463 ,  C03C3/06 ,  C03C2201/12 ,  C03C2203/46 ,  C23C16/401 ,  C23C16/46 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31625

Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate. This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers. An undoped silicon glass (USG) liner protects the substrate from corrosive attack. The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 0.8 &mgr;m with an aspect ratio of up to 4.5:1.

Abstract translation: 一系列工艺步骤在衬底上形成氟化硅玻璃（FSG）层。 该层在层中不太可能形成雾状或气泡，并且在后续处理步骤中比其他FSG层更不可能解吸水蒸汽。 未掺杂的硅玻璃（USG）衬垫可保护基材免受腐蚀性侵袭。 USG衬垫和FSG层沉积在相对热的晶片表面上，并且可以填充窄至0.8μm的衬底上的沟槽，纵横比高达4.5:1。

公开(公告)号：US6136685A

公开(公告)日：2000-10-24

申请号：US868595

申请日：1997-06-03

Applicant: Pravin Narwankar ,  Laxman Murugesh ,  Turgut Sahin ,  Maciek Orczyk ,  Jianmin Qiao

Inventor： Pravin Narwankar ,  Laxman Murugesh ,  Turgut Sahin ,  Maciek Orczyk ,  Jianmin Qiao

IPC: H01L21/205 ,  C23C16/40 ,  C23C16/505 ,  C23C16/52 ,  H01L21/31 ,  H01L21/316 ,  H01L21/4763

CPC classification number: H01L21/02131 ,  C23C16/401 ,  C23C16/505 ,  C23C16/52 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31629

Abstract: An insulating film with a low dielectric constant is more quickly formed on a substrate by reducing the co-etch rate as the film is deposited. The process gas is formed into a plasma from silicon-containing and fluorine-containing gases. The plasma is biased with an RF field to enhance deposition of the film. Deposition and etching occur simultaneously. The relative rate of deposition to etching is increased in the latter portion of the deposition process by decreasing the bias RF power, which decreases the surface temperature of the substrate and decreases sputtering and etching activities. Processing time is reduced compared to processes with fixed RF power levels. Film stability, retention of water by the film, and corrosion of structures on the substrate are all improved. The film has a relatively uniform and low dielectric constant and may fill trenches with aspect ratios of at least 4:1 and gaps less than 0.5 .mu.m.

Abstract translation: 当薄膜沉积时，通过降低共蚀刻速率，在衬底上更迅速地形成具有低介电常数的绝缘膜。 工艺气体由含硅和含氟气体形成等离子体。 等离子体被RF场偏置以增强膜的沉积。 沉积和蚀刻同时发生。 通过降低偏压RF功率，沉积过程的后一部分，相对于蚀刻的相对速率增加，这降低了衬底的表面温度并降低了溅射和蚀刻活性。 与具有固定RF功率级别的处理相比，处理时间缩短。 薄膜的稳定性，薄膜的水分保持性以及基板上的结构的腐蚀都得到改善。 该膜具有相对均匀和低的介电常数，并且可以填充具有至少4:1的纵横比和小于0.5μm的间隙的沟槽。

公开(公告)号：US5937323A

公开(公告)日：1999-08-10

申请号：US868286

申请日：1997-06-03

Applicant: Maciek Orczyk ,  Laxman Murugesh ,  Pravin Narwankar

Inventor： Maciek Orczyk ,  Laxman Murugesh ,  Pravin Narwankar

IPC: H01L21/31 ,  C03C3/06 ,  C23C16/40 ,  C23C16/46 ,  H01L21/3105 ,  H01L21/316

CPC classification number: C23C16/463 ,  C03C3/06 ,  C23C16/401 ,  C23C16/46 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3105 ,  H01L21/31625 ,  C03C2201/12 ,  C03C2203/46

Abstract: A sequence of process steps forms a fluorinated silicon glass (FSG) layer on a substrate. This layer is much less likely to form a haze or bubbles in the layer, and is less likely to desorb water vapor during subsequent processing steps than other FSG layers. An undoped silicon glass (USG) liner protects the substrate from corrosive attack. The USG liner and FSG layers are deposited on a relatively hot wafer surface and can fill trenches on the substrate as narrow as 0.8 .mu.m with an aspect ratio of up to 4.5:1.

Abstract translation: 一系列工艺步骤在衬底上形成氟化硅玻璃（FSG）层。 该层在层中不太可能形成雾状或气泡，并且在后续处理步骤中比其他FSG层更不可能解吸水蒸汽。 未掺杂的硅玻璃（USG）衬垫可保护基材免受腐蚀性侵袭。 USG衬垫和FSG层沉积在相对热的晶片表面上，并且可以将衬底上的沟槽填充到0.8μm的窄度，纵横比高达4.5:1。

公开(公告)号：US5811356A

公开(公告)日：1998-09-22

申请号：US704428

申请日：1996-08-19

Applicant: Laxman Murugesh ,  Pravin Narwankar ,  Turgut Sahin ,  Kent Rossman

Inventor： Laxman Murugesh ,  Pravin Narwankar ,  Turgut Sahin ,  Kent Rossman

IPC: C23C16/44 ,  C23C16/50 ,  C23C16/517 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/00

CPC classification number: H01J37/32862 ,  C23C16/4401 ,  C23C16/4404 ,  C23C16/517 ,  H01J37/321 ,  Y10S438/905

Abstract: The present invention provides a method and apparatus for reducing the concentration of mobile ion and metal contaminants in a processing chamber by increasing the bias RF power density to greater than 0.051 W/mm.sup.2 and increasing the season time to greater than 30 seconds, during a chamber seasoning step. The method of performing a season step in a chamber by depositing a deposition material under the combined conditions of a bias RF power density of about 0.095 W/mm.sup.2 and a season time of from about 50 to about 70 seconds, reduces the mobile ion and metal contaminant concentrations within the chamber by about one order of magnitude.

Abstract translation: 本发明提供了一种通过在室内增加偏压RF功率密度大于0.051W / mm 2并将季节时间增加到大于30秒来减少处理室中的移动离子和金属污染物的浓度的方法和装置 调味步骤 通过在约0.095W / mm 2的偏置RF功率密度和约50至约70秒的季节时间的组合条件下沉积沉积材料在室中进行季节步骤的方法减少了移动离子和金属 室内的污染物浓度大约一个数量级。

公开(公告)号：US06200911B1

公开(公告)日：2001-03-13

申请号：US09264990

申请日：1998-04-21

Applicant: Pravin Narwankar ,  Sameer Desai ,  Walter Zygmunt ,  Turgut Sahin ,  Laxman Murugesh

Inventor： Pravin Narwankar ,  Sameer Desai ,  Walter Zygmunt ,  Turgut Sahin ,  Laxman Murugesh

IPC: H01L2131

CPC classification number: C23C16/4411 ,  C23C16/045 ,  C23C16/4405 ,  C23C16/4412 ,  C23C16/46 ,  C23C16/507 ,  C23C16/52 ,  H01J37/321 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/76224

Abstract: A method and apparatus for modifying the profile of narrow, high-aspect-ratio gaps on a semiconductor substrate are used to fill the gaps in a void-free manner. Differential heating characteristics of a substrate in a high-density plasma chemical vapor deposition (HDP-CVD) system helps to prevent the gaps from being pinched off before they are filled. The power distribution between coils forming the plasma varies the angular dependence of the sputter etch component of the plasma, and thus may be used to modify the gap profile, independently or in conjunction with differential heating. A heat source may be applied to the backside of a substrate during the concurrent deposition/etch process to further enhance the profile modification characteristics of differential heating.

公开(公告)号：US06579811B2

公开(公告)日：2003-06-17

申请号：US09745918

申请日：2000-12-20

Applicant: Pravin Narwankar ,  Sameer Desai ,  Walter Zygmunt ,  Turgut Sahin ,  Laxman Murugesh

Inventor： Pravin Narwankar ,  Sameer Desai ,  Walter Zygmunt ,  Turgut Sahin ,  Laxman Murugesh

IPC: H01L2131

CPC classification number: C23C16/4411 ,  C23C16/045 ,  C23C16/4405 ,  C23C16/4412 ,  C23C16/46 ,  C23C16/507 ,  C23C16/52 ,  H01J37/321 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/76224

Abstract: A method and apparatus for modifying the profile of narrow, high-aspect-ratio gaps on a semiconductor substrate are used to fill the gaps in a void-free manner. Differential heating characteristics of a substrate in a high-density plasma chemical vapor deposition (HDP-CVD) system helps to prevent the gaps from being pinched off before they are filled. The power distribution between coils forming the plasma varies the angular dependence of the sputter etch component of the plasma, and thus may be used to modify the gap profile, independently or in conjunction with differential heating. A heat source may be applied to the backside of a substrate during the concurrent deposition/etch process to further enhance the profile modification characteristics of differential heating.

Abstract translation: 用于改变半导体衬底上窄，高纵横比间隙的轮廓的方法和装置用于以无空隙的方式填充间隙。 高密度等离子体化学气相沉积（HDP-CVD）系统中的衬底的差分加热特性有助于防止间隙在填充之前被夹住。 形成等离子体的线圈之间的功率分布改变了等离子体的溅射蚀刻部件的角度依赖性，并且因此可以独立地或与差分加热一起用于修改间隙分布。 在同时的沉积/蚀刻过程期间，可以将热源施加到衬底的背面，以进一步增强差分加热的轮廓修改特性。

公开(公告)号：US20060062917A1

公开(公告)日：2006-03-23

申请号：US11223896

申请日：2005-09-09

Applicant: Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

Inventor： Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

IPC: C23C16/00

CPC classification number: C23C16/308 ,  C23C16/401 ,  C23C16/56

Abstract: In one embodiment, a method for forming a morphologically stable dielectric material is provided which includes exposing a substrate to a hafnium precursor, a silicon precursor and an oxidizing gas to form hafnium silicate material during a chemical vapor deposition (CVD) process and subsequently and optionally exposing the substrate to a post deposition anneal, a nitridation process and a thermal annealing process. In some examples, the hafnium and silicon precursors used during a metal-organic CVD (MOCVD) process are alkylamino compounds, such as tetrakis(diethylamino)hafnium (TDEAH) and tris(dimethylamino)silane (Tris-DMAS). In another embodiment, other metal precursors may be used to form a variety of metal silicates containing tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof.

Abstract translation: 在一个实施方案中，提供了一种用于形成形态稳定的电介质材料的方法，其包括在化学气相沉积（CVD）工艺期间将衬底暴露于铪前体，硅前体和氧化气体以形成硅酸铪材料，随后和任选地 将衬底暴露于后沉积退火，氮化工艺和热退火工艺。 在一些实例中，在金属 - 有机CVD（MOCVD）方法中使用的铪和硅前体是烷基氨基化合物，例如四（二乙基氨基）铪（TDEAH）和三（二甲氨基）硅烷（Tris-DMAS）。 在另一个实施方案中，其它金属前体可用于形成含有钽，钛，铝，锆，镧或其组合的各种金属硅酸盐。

公开(公告)号：US20050260357A1

公开(公告)日：2005-11-24

申请号：US10851514

申请日：2004-05-21

Applicant: Christopher Olsen ,  Pravin Narwankar ,  Shreyas Kher ,  Randhir Thakur ,  Shankar Muthukrishnan ,  Philip Kraus

Inventor： Christopher Olsen ,  Pravin Narwankar ,  Shreyas Kher ,  Randhir Thakur ,  Shankar Muthukrishnan ,  Philip Kraus

IPC: C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  B05D7/00

CPC classification number: H01L21/3141 ,  C23C16/401 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/56 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31637 ,  H01L21/31645 ,  H01L29/517

Abstract: In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.

Abstract translation: 在一个实施例中，提供了一种在衬底上形成电介质堆叠的方法，其包括在衬底表面上沉积介电材料的第一层，将第一层暴露于氮化工艺，将第二层介电材料沉积在 第一层，将第二层暴露于氮化工艺，并将衬底暴露于退火工艺。 在另一个实施例中，提供了一种用于在衬底上形成介电材料的方法，其包括在衬底表面上沉积基本上不含硅的金属氧化物层，将金属氧化物层暴露于氮化工艺，以及将衬底暴露于退火工艺 。

公开(公告)号：US20050260347A1

公开(公告)日：2005-11-24

申请号：US10851561

申请日：2004-05-21

Applicant: Pravin Narwankar ,  Gregg Higashi

Inventor： Pravin Narwankar ,  Gregg Higashi

IPC: C23C16/30 ,  H01L21/314 ,  C23C16/00

CPC classification number: H01L21/3141 ,  C23C16/401 ,  H01L21/3143

Abstract: In one embodiment, a method for depositing a capping layer on a dielectric layer in a process chamber is provided which includes depositing the dielectric layer on a substrate surface, depositing a silicon-containing layer by an ALD process, comprising alternately pulsing a silicon precursor and an oxidizing gas into the process chamber, and exposing the silicon-containing layer to a nitridation process. In another embodiment, a method for depositing a silicon-containing capping layer on a dielectric layer in a process chamber by an ALD process is provided which includes flowing a silicon precursor into the process chamber, purging the process chamber with a purge gas, flowing an oxidizing gas comprising water formed by flowing a H2 gas and an oxygen-containing gas through a water vapor generator, and purging the process chamber with the purge gas.

Abstract translation: 在一个实施例中，提供了一种用于在处理室中的电介质层上沉积覆盖层的方法，其包括在基底表面上沉积电介质层，通过ALD工艺沉积含硅层，包括交替地脉冲硅前体和 氧化气体进入处理室，并将含硅层暴露于氮化过程。 在另一个实施例中，提供了一种通过ALD工艺在处理室中的电介质层上沉积含硅覆盖层的方法，其包括使硅前体流入处理室，用净化气体吹扫处理室， 包括通过使H 2气体和含氧气体流过水蒸气发生器而形成的水的氧化气体，以及用吹扫气体吹扫处理室。

公开(公告)号：US06548368B1

公开(公告)日：2003-04-15

申请号：US09644941

申请日：2000-08-23

Applicant: Pravin Narwankar ,  Ravi Rajagopalan

Inventor： Pravin Narwankar ,  Ravi Rajagopalan

IPC: H01L2120

CPC classification number: H01L28/40 ,  H01L21/3143 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/3185

Abstract: Provided is a method of integrating Ta2O5 into an MIS stack capacitor for a semiconductor device by forming a thin SiON layer at the Si/TaO interface using low temperature remote plasma oxidation anneal. Also provided is a method of forming an MIS stack capacitor with improved electrical performance by treating SiO2 with remote plasma nitridation or SiN layer with rapid thermal oxidation or RPO to form a SiON layer prior to Ta2O5 deposition with TAT-DMAE, TAETO or any other Ta-containing precursor.

Abstract translation: 提供了一种通过使用低温远程等离子体氧化退火在Si / TaO界面处形成薄SiON层来将Ta 2 O 5集成到用于半导体器件的MIS堆叠电容器中的方法。 还提供了一种通过用远程等离子体氮化处理SiO 2或具有快速热氧化或RPO的SiN层来形成具有改进的电性能的MIS堆叠电容器的方法，以在与TAT-DMAE，TAETO或任何其它Ta的Ta 2 O 5沉积之前形成SiON层 含有前体。