公开(公告)号：US20180090429A1

公开(公告)日：2018-03-29

申请号：US15563214

申请日：2015-07-03

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya KOBAYASHI ,  Soshi KURODA

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A BGA 9 includes a wiring substrate 2, a semiconductor chip 1 fixed on the wiring substrate 2, a sealing body 4 that seals the semiconductor chip 1, and a plurality of solder balls 5 provided on a lower surface of the wiring substrate 2. A degree of flatness of an upper surface 2ia of a first wiring layer 2i of the wiring substrate 2 of the BGA 9 is lower than a degree of flatness of a lower surface 2ib, and a first pattern 2jc provided in a second wiring layer 2j is arranged at a position overlapping a first pattern 2ic provided in the first wiring layer 2i. Also, an area of the first pattern 2ic provided in the first wiring layer 2i is larger than an area of a plurality of (for example, two) second patterns 2jd provided in the second wiring layer 2j in a plan view, and a first opening portion 2jm through which a part of a second insulating layer 2h is exposed is formed in the first pattern 2jc provided in the second wiring layer 2j.

公开(公告)号：US20210057361A1

公开(公告)日：2021-02-25

申请号：US16910225

申请日：2020-06-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Seiya ISOZAKI ,  Tatsuya KOBAYASHI ,  Kota JINNO

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78

Abstract: A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.

公开(公告)号：US20180315691A1

公开(公告)日：2018-11-01

申请号：US15955090

申请日：2018-04-17

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya KOBAYASHI

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85013 ,  H01L2224/92247 ,  H01L2924/3512 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/10378 ,  H05K2201/10734 ,  H01L2924/00

Abstract: An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.

公开(公告)号：US20180033709A1

公开(公告)日：2018-02-01

申请号：US15662127

申请日：2017-07-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Soshi KURODA ,  Tatsuya KOBAYASHI ,  Takanori AOKI

IPC: H01L23/31 ,  H01L23/498 ,  H01L29/06 ,  H01L21/56 ,  H01L23/535 ,  H01L21/66 ,  H01L23/29 ,  H01L21/78 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L22/32 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/535 ,  H01L23/562 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L29/0649 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/06135 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/0665 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0655

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.