公开(公告)号：US20140273353A1

公开(公告)日：2014-09-18

申请号：US14294029

申请日：2014-06-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masatoshi YASUNAGA ,  Hironori MATSUSHIMA ,  Kenya HIRONAGA ,  Soshi KURODA

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/85 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/04 ,  H01L24/05 ,  H01L24/27 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/32145 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48482 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48844 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2924/20758 ,  H01L2924/2075 ,  H01L2924/00015

Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.

Abstract translation: 为了提高使用由铜制成的线进行引线接合的半导体器件的可靠性。 半导体器件被配置为使得铜线的端部（宽宽度部分）中的一个通过形成在半导体器件的半导体芯片的主表面（第一主表面）上的焊盘（电极焊盘）上的凸块接合 。 凸起由金制成，其是具有低于铜的硬度的金属材料，并且凸块的宽度比电线的宽幅部分的宽度窄。

公开(公告)号：US20140073068A1

公开(公告)日：2014-03-13

申请号：US14024896

申请日：2013-09-12

Applicant: Renesas Electronics Corporation

Inventor： Kenya HIRONAGA ,  Masatoshi YASUNAGA ,  Tatsuya HIRAI ,  Soshi KURODA

IPC: H01L23/00 ,  H01L21/50

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/8512 ,  H01L2224/8513 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract translation: 提供了具有提高的可靠性的半导体器件。 在本实施方式的半导体装置中，与设置在阻焊剂中的开口露出的带状配线的接合面相对应设置标记。 结果，在引线接合区域的对准步骤中，可以不使用形成在阻焊剂中的开口的端部来调整引线接合区域的坐标位置，而是将与引线接合区域相对应的标记作为 参考。 此外，在本实施方式的半导体装置中，形成作为特征图案的标记。 这允许根据相机识别来调整引线接合区域。

公开(公告)号：US20170162539A1

公开(公告)日：2017-06-08

申请号：US15414919

申请日：2017-01-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenya HIRONAGA ,  Masatoshi YASUNAGA ,  Tatsuya HIRAI ,  Soshi KURODA

IPC: H01L23/00 ,  H01L21/48

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/8512 ,  H01L2224/8513 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

公开(公告)号：US20180090429A1

公开(公告)日：2018-03-29

申请号：US15563214

申请日：2015-07-03

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya KOBAYASHI ,  Soshi KURODA

IPC: H01L23/498 ,  H01L23/367 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A BGA 9 includes a wiring substrate 2, a semiconductor chip 1 fixed on the wiring substrate 2, a sealing body 4 that seals the semiconductor chip 1, and a plurality of solder balls 5 provided on a lower surface of the wiring substrate 2. A degree of flatness of an upper surface 2ia of a first wiring layer 2i of the wiring substrate 2 of the BGA 9 is lower than a degree of flatness of a lower surface 2ib, and a first pattern 2jc provided in a second wiring layer 2j is arranged at a position overlapping a first pattern 2ic provided in the first wiring layer 2i. Also, an area of the first pattern 2ic provided in the first wiring layer 2i is larger than an area of a plurality of (for example, two) second patterns 2jd provided in the second wiring layer 2j in a plan view, and a first opening portion 2jm through which a part of a second insulating layer 2h is exposed is formed in the first pattern 2jc provided in the second wiring layer 2j.

公开(公告)号：US20180033709A1

公开(公告)日：2018-02-01

申请号：US15662127

申请日：2017-07-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Soshi KURODA ,  Tatsuya KOBAYASHI ,  Takanori AOKI

IPC: H01L23/31 ,  H01L23/498 ,  H01L29/06 ,  H01L21/56 ,  H01L23/535 ,  H01L21/66 ,  H01L23/29 ,  H01L21/78 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L22/32 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/535 ,  H01L23/562 ,  H01L23/585 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L29/0649 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/0612 ,  H01L2224/06135 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49431 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/0665 ,  H01L2924/10155 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/0655

Abstract: To provide a semiconductor device having improved reliability. The semiconductor device has a wiring board, bonding land, semiconductor chip mounted on the wiring board via an adhesive layer and having a pad electrode, bonding wire connecting the pad electrode with the bonding land, and sealing body. The sealing body is, in a circuit formation region, in contact with an organic protection film and, in a scribe region and a region between the pad electrode and the scribe region, in contact with a surface protection film while not in contact with the organic protection film. A first side surface is closer to the circuit formation region side than a second one. The adhesive layer covers entirety of the semiconductor chip back surface and the second side surface of the semiconductor chip. The first side surface is in contact with the sealing body without being covered with the adhesive layer.

公开(公告)号：US20160163625A1

公开(公告)日：2016-06-09

申请号：US15041858

申请日：2016-02-11

Applicant: Renesas Electronics Corporation

Inventor： Yosuke IMAZEKI ,  Soshi KURODA

IPC: H01L23/498 ,  H01L25/065

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/065 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0612 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48824 ,  H01L2224/48844 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83101 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2224/4554

Abstract: A semiconductor device includes a wiring substrate having an upper surface, a plurality of terminals formed on the upper surface, and a lower surface opposite to the upper surface, a first semiconductor chip having a first main surface, a plurality of first electrodes formed on the first main surface, and a first rear surface opposite to the first main surface, and mounted over the upper surface of the wiring substrate such that the first rear surface of the first semiconductor chip faces the upper surface of the wiring substrate, and a plurality of wires electrically connected with the plurality of terminals, respectively.

Abstract translation: 半导体器件包括具有上表面的布线基板，形成在上表面上的多个端子和与上表面相对的下表面，第一半导体芯片，具有第一主表面，多个第一电极形成在第一主表面上 第一主表面和与第一主表面相对的第一后表面，并且安装在布线基板的上表面上，使得第一半导体芯片的第一后表面面向布线基板的上表面，并且多个 电线分别与多个端子电连接。

公开(公告)号：US20150371967A1

公开(公告)日：2015-12-24

申请号：US14841409

申请日：2015-08-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kenya HIRONAGA ,  Masatoshi YASUNAGA ,  Tatsuya HIRAI ,  Soshi KURODA

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/50 ,  H01L23/3107 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83192 ,  H01L2224/8512 ,  H01L2224/8513 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided is a semiconductor device having improved reliability. In the semiconductor device in an embodiment, a mark is provided correspondingly to the bonding area of a belt-like wiring exposed from an opening provided in a solder resist. As a result, in an alignment step for the wire bonding area, the coordinate position of the wire bonding area can be adjusted using not the end portion of the opening formed in the solder resist, but the mark formed correspondingly to the wire bonding area as a reference. Also, in the semiconductor device in the embodiment, the mark serving as a characteristic pattern is formed. This allows the wire bonding area to be adjusted based on camera recognition.

Abstract translation: 提供了具有提高的可靠性的半导体器件。 在本实施方式的半导体装置中，与设置在阻焊剂中的开口露出的带状配线的接合面相对应设置标记。 结果，在引线接合区域的对准步骤中，可以不使用形成在阻焊剂中的开口的端部来调整引线接合区域的坐标位置，而是将与引线接合区域相对应的标记作为 参考。 此外，在本实施方式的半导体装置中，形成作为特征图案的标记。 这允许根据相机识别来调整引线接合区域。