公开(公告)号：US20130256906A1

公开(公告)日：2013-10-03

申请号：US13767940

申请日：2013-02-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo Mori ,  Kazuki Fukuoka ,  Naozumi Morino ,  Yoshinori Deguchi

IPC: H01L23/538 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/02697 ,  H01L21/768 ,  H01L22/32 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

公开(公告)号：US09171767B2

公开(公告)日：2015-10-27

申请号：US14536620

申请日：2014-11-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo Mori ,  Kazuki Fukuoka ,  Naozumi Morino ,  Yoshinori Deguchi

IPC: H01L23/48 ,  H01L21/66 ,  H01L23/538 ,  H01L21/02 ,  H01L23/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/02697 ,  H01L21/768 ,  H01L22/32 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract translation: 一种半导体器件包括：基板，包括形成有电路元件的电路区域;多层布线层，其形成在所述基板上并且由多个布线层和多​​个层叠的通孔层构成;电极焊盘， 形成在多层布线层上。 在电极焊盘的平面图中，在电极焊盘和第一电路区域彼此重叠的区域中，在作为多个布线层的顶层的第一布线层的区域中形成层间绝缘膜。

公开(公告)号：US08896129B2

公开(公告)日：2014-11-25

申请号：US13767940

申请日：2013-02-15

Applicant: Renesas Electronics Corporation

Inventor： Ryo Mori ,  Kazuki Fukuoka ,  Naozumi Morino ,  Yoshinori Deguchi

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/02 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/02697 ,  H01L21/768 ,  H01L22/32 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

Abstract translation: 一种半导体器件包括：基板，包括形成有电路元件的电路区域;多层布线层，其形成在所述基板上并且由多个布线层和多​​个层叠的通孔层构成;电极焊盘， 形成在多层布线层上。 在电极焊盘的平面图中，在电极焊盘和第一电路区域彼此重叠的区域中，在作为多个布线层的顶层的第一布线层的区域中形成层间绝缘膜。

公开(公告)号：US10818601B1

公开(公告)日：2020-10-27

申请号：US16911852

申请日：2020-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori Deguchi ,  Akinobu Watanabe

IPC: H01L23/535 ,  H01L23/522 ,  H01L21/768 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L23/58 ,  H01L21/3205

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

公开(公告)号：US10141295B2

公开(公告)日：2018-11-27

申请号：US15730977

申请日：2017-10-12

Applicant: Renesas Electronics Corporation

Inventor： Bunji Yasumura ,  Yoshinori Deguchi ,  Fumikazu Takei ,  Akio Hasebe ,  Naohiro Makihira ,  Mitsuyuki Kubo

IPC: H01L21/30 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00 ,  H01L21/66 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

公开(公告)号：US20160027731A1

公开(公告)日：2016-01-28

申请号：US14875335

申请日：2015-10-05

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ryo Mori ,  Kazuki Fukuoka ,  Naozumi Morino ,  Yoshinori Deguchi

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/02697 ,  H01L21/768 ,  H01L22/32 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate including a circuit region where a circuit element is formed, a multilayer wiring layer that is formed on the substrate and composed of a plurality of wiring layers and a plurality of via layers that are laminated, and an electrode pad that is formed on the multilayer wiring layer. An interlayer insulating film is formed in a region of a first wiring layer that is a top layer of the plurality of wiring layers, in the region the electrode pad and the first circuit region overlapping each other in a planar view of the electrode pad.

公开(公告)号：US08945953B2

公开(公告)日：2015-02-03

申请号：US14133614

申请日：2013-12-18

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L21/66

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract translation: 提供了一种制造半导体器件的方法，该半导体器件包括测试每个通孔的步骤。 进行第二探针测试以检查形成在晶片表面一侧的多个铜柱形凸块之间的电耦合状态，并且电耦合到金属层和形成在背面侧的多个凸点 并且通过探测背面一侧的每个凸块，同时在铜柱凸起（电极）之间短路，通过多个通孔电耦合到金属层（也是另一金属层）。 通过该测试，检查背面侧的凸块（电极）之间的导通。

公开(公告)号：US11456264B2

公开(公告)日：2022-09-27

申请号：US17148923

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshiaki Sato ,  Mitsunobu Wansawa ,  Akira Matsumoto ,  Yoshinori Deguchi ,  Kentaro Saito

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  G11C16/04 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device according to one embodiment, after a semiconductor wafer including a non-volatile memory, a bonding pad and an insulating film comprised of an organic material is provided, a probe needle is contacted to a surface of the bonding pad located in a second region, and a data is written to the non-volatile memory. Here, the insulating film is formed by performing a first heat treatment to the organic material. Also, after a second heat treatment is performed to the semiconductor wafer, and the non-volatile memory to which the data is written is checked, a barrier layer and a first solder material are formed on the surface of the bonding pad located in a first region by using an electroplating method. Further, a bump electrode is formed in the first region by performing a third heat treatment to the first solder material.

公开(公告)号：US09053954B2

公开(公告)日：2015-06-09

申请号：US14194874

申请日：2014-03-03

Applicant: Renesas Electronics Corporation

Inventor： Bunji Yasumura ,  Yoshinori Deguchi ,  Fumikazu Takei ,  Akio Hasebe ,  Naohiro Makihira ,  Mitsuyuki Kubo

IPC: H01L21/30 ,  H01L25/065 ,  H01L23/544 ,  H01L21/66

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L22/12 ,  H01L22/14 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2223/54493 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06131 ,  H01L2224/11009 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00

Abstract: To improve the assemblability of a semiconductor device.When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy.

Abstract translation: 提高半导体器件的组装性。 当存储器芯片安装在逻辑芯片上时，将形成在逻辑芯片的背面的识别标记的识别范围成像，识别范围的形状，逻辑芯片的多个凸点与 基于识别的结果执行上述存储芯片的多个投影电极，并且将上述存储芯片安装在逻辑芯片上。 此时，识别范围的形状与凸块的阵列形状的任何部分不同，结果，可以可靠地识别识别范围形状的识别标记，并且逻辑的凸块的对准 高精度地执行上述存储芯片的芯片和投影电极。

公开(公告)号：US20150111317A1

公开(公告)日：2015-04-23

申请号：US14583693

申请日：2014-12-27

Applicant: Renesas Electronics Corporation

Inventor： Akio Hasebe ,  Naohiro Makihira ,  Bunji Yasumura ,  Mitsuyuki Kubo ,  Fumikazu Takei ,  Yoshinori Deguchi

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/66

CPC classification number: H01L24/89 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L22/14 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/08235 ,  H01L2224/1146 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/8036 ,  H01L2224/8085 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Provided is a method of manufacturing a semiconductor device including a step of testing every one of through-electrodes. A second probe test is conducted to check an electrical coupling state between a plurality of copper post bumps formed on the side of the surface of a wafer and electrically coupled to a metal layer and a plurality of bumps formed on the side of the back surface of the wafer and electrically coupled to the metal layer (also another metal layer) via a plurality of through-electrodes by probing to each of the bumps on the side of the back surface while short-circuiting between the copper post bumps (electrodes). By this test, conduction between the bumps (electrodes) on the back surface side is checked.

Abstract translation: 提供了一种制造半导体器件的方法，该半导体器件包括测试每个通孔的步骤。 进行第二探针测试以检查形成在晶片表面一侧的多个铜柱形凸块之间的电耦合状态，并且电耦合到金属层和形成在背面侧的多个凸点 并且通过探测背面一侧的每个凸块，同时在铜柱凸起（电极）之间短路，通过多个通孔电耦合到金属层（也是另一金属层）。 通过该测试，检查背面侧的凸块（电极）之间的导通。